From: Richard Earnshaw Date: Fri, 5 Jan 2001 16:15:59 +0000 (+0000) Subject: arm.md (ldmsi_postinc): Avoid use of match_dup between input and output operands. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b08889882442e6b36fe49033fa658ec6cc489199;p=gcc.git arm.md (ldmsi_postinc): Avoid use of match_dup between input and output operands. * arm.md (ldmsi_postinc): Avoid use of match_dup between input and output operands. Use arm_hard_register_operand for operand 4. (stmsi_postinc): Similarly. (ldmsi): Use arm_hard_register_operand for opernand 2. (stmsi): Similarly. * arm.c (arm_hard_register_operand): New function. * arm-protos.h (arm_hard_register_operand): Prototype it. * arm.h (HARD_REGNO_RENAME_OK): Define. From-SVN: r38712 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6a12ecae04c..7f44b557e90 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,15 @@ +2001-01-05 Richard Earnshaw + + * arm.md (ldmsi_postinc): Avoid use of match_dup between input and + output operands. Use arm_hard_register_operand for operand 4. + (stmsi_postinc): Similarly. + (ldmsi): Use arm_hard_register_operand for opernand 2. + (stmsi): Similarly. + * arm.c (arm_hard_register_operand): New function. + * arm-protos.h (arm_hard_register_operand): Prototype it. + + * arm.h (HARD_REGNO_RENAME_OK): Define. + Fri Jan 5 16:29:49 MET 2001 Jan Hubicka * simplify-rtx.c (cfc_args): add "unordered" field. diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index ac3713adda0..087d8cdb61f 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -1,5 +1,5 @@ /* Prototypes for exported functions defined in arm.c and pe.c - Copyright (C) 1999, 2000 Free Software Foundation, Inc. + Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc. Contributed by Richard Earnshaw (rearnsha@arm.com) Minor hacks by Nick Clifton (nickc@cygnus.com) @@ -60,6 +60,7 @@ extern int neg_const_double_rtx_ok_for_fpu PARAMS ((rtx)); /* Predicates. */ extern int s_register_operand PARAMS ((rtx, enum machine_mode)); +extern int arm_hard_register_operand PARAMS ((rtx, enum machine_mode)); extern int f_register_operand PARAMS ((rtx, enum machine_mode)); extern int reg_or_int_operand PARAMS ((rtx, enum machine_mode)); extern int arm_reload_memory_operand PARAMS ((rtx, enum machine_mode)); @@ -129,6 +130,7 @@ extern const char * output_return_instruction PARAMS ((rtx, int, int)); extern void arm_poke_function_name PARAMS ((FILE *, char *)); extern void output_arm_prologue PARAMS ((FILE *, int)); extern void arm_print_operand PARAMS ((FILE *, rtx, int)); +extern void arm_print_operand_address PARAMS ((FILE *, rtx)); extern void arm_final_prescan_insn PARAMS ((rtx)); extern int arm_go_if_legitimate_address PARAMS ((enum machine_mode, rtx)); extern int arm_debugger_arg_offset PARAMS ((int, rtx)); diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index d71dcd1c1db..16479d4fba7 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -1,5 +1,5 @@ /* Output routines for GCC for ARM. - Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000 + Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) and Martin Simmons (@harleqn.co.uk). @@ -2861,6 +2861,19 @@ s_register_operand (op, mode) || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); } +/* A hard register operand (even before reload. */ +int +arm_hard_register_operand (op, mode) + register rtx op; + enum machine_mode mode; +{ + if (GET_MODE (op) != mode && mode != VOIDmode) + return 0; + + return (GET_CODE (op) == REG + && REGNO (op) < FIRST_PSEUDO_REGISTER); +} + /* Only accept reg, subreg(reg), const_int. */ int diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 6170187f3b5..43d31386b3a 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -1319,6 +1319,17 @@ enum reg_class : \ ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2) +/* Register Renaming Parameters. */ + +/* A C expression that is nonzero if hard register number TO can be + considered for use as a rename register for FROM. + + If the return register isn't already live, we mustn't use it. */ + +#define HARD_REGNO_RENAME_OK(FROM,TO) \ + ((TO) != LR_REGNUM || regs_ever_live[LR_REGNUM]) + + /* Stack layout; function entry, exit and calling. */ /* Define this if pushing a word on the stack diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 75696949677..d391dae6f6b 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -1,5 +1,5 @@ ;;- Machine description for ARM for GNU compiler -;; Copyright 1991, 1993, 1994, 1995, 1996, 1996, 1997, 1998, 1999, 2000 +;; Copyright 1991, 1993, 1994, 1995, 1996, 1996, 1997, 1998, 1999, 2000, 2001 ;; Free Software Foundation, Inc. ;; Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) ;; and Martin Simmons (@harleqn.co.uk). @@ -5187,12 +5187,12 @@ (define_insn "*ldmsi_postinc" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "s_register_operand" "+r") - (plus:SI (match_dup 1) - (match_operand:SI 2 "const_int_operand" "n"))) - (set (match_operand:SI 3 "s_register_operand" "=r") - (mem:SI (match_dup 1)))])] - "TARGET_ARM && (INTVAL (operands[2]) == 4 * (XVECLEN (operands[0], 0) - 1))" + [(set (match_operand:SI 1 "s_register_operand" "=r") + (plus:SI (match_operand:SI 2 "s_register_operand" "1") + (match_operand:SI 3 "const_int_operand" "n"))) + (set (match_operand:SI 4 "arm_hard_register_operand" "") + (mem:SI (match_dup 2)))])] + "TARGET_ARM && (INTVAL (operands[3]) == 4 * (XVECLEN (operands[0], 0) - 1))" "* { rtx ops[3]; @@ -5214,7 +5214,7 @@ (define_insn "*ldmsi" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "s_register_operand" "=r") + [(set (match_operand:SI 1 "arm_hard_register_operand" "") (mem:SI (match_operand:SI 2 "s_register_operand" "r")))])] "TARGET_ARM" "* @@ -5263,12 +5263,12 @@ (define_insn "*stmsi_postinc" [(match_parallel 0 "store_multiple_operation" - [(set (match_operand:SI 1 "s_register_operand" "+r") - (plus:SI (match_dup 1) - (match_operand:SI 2 "const_int_operand" "n"))) - (set (mem:SI (match_dup 1)) - (match_operand:SI 3 "s_register_operand" "r"))])] - "TARGET_ARM && (INTVAL (operands[2]) == 4 * (XVECLEN (operands[0], 0) - 1))" + [(set (match_operand:SI 1 "s_register_operand" "=r") + (plus:SI (match_operand:SI 2 "s_register_operand" "1") + (match_operand:SI 3 "const_int_operand" "n"))) + (set (mem:SI (match_dup 2)) + (match_operand:SI 4 "arm_hard_register_operand" ""))])] + "TARGET_ARM && (INTVAL (operands[3]) == 4 * (XVECLEN (operands[0], 0) - 1))" "* { rtx ops[3]; @@ -5295,8 +5295,8 @@ (define_insn "*stmsi" [(match_parallel 0 "store_multiple_operation" - [(set (mem:SI (match_operand:SI 2 "s_register_operand" "r")) - (match_operand:SI 1 "s_register_operand" "r"))])] + [(set (mem:SI (match_operand:SI 1 "s_register_operand" "r")) + (match_operand:SI 2 "arm_hard_register_operand" ""))])] "TARGET_ARM" "* {