From: Pat Haugen <pthaugen@linux.ibm.com>
Date: Thu, 10 Sep 2020 14:46:46 +0000 (-0500)
Subject: Fix instruction types.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b0894ae0e7b269d15932e7ddba1d56bb4f48931e;p=gcc.git

Fix instruction types.

I noticed that some of the VSR<->GPR move instructions are not typed correctly. This patch fixes those instructions so that the scheduler treats them with the correct latency.

2020-09-10  Pat Haugen  <pthaugen@linux.ibm.com>

gcc/
	* config/rs6000/rs6000.md
	(lfiwzx, floatunssi<mode>2_lfiwzx, p8_mtvsrwz, p8_mtvsrd_sf): Fix insn
	type.
	* config/rs6000/vsx.md
	(vsx_concat_<mode>, vsx_splat_<mode>_reg, vsx_splat_v4sf): Likewise.
---

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 43b620ae1c0..f902c864c26 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -5483,7 +5483,7 @@
    lxsiwzx %x0,%y1
    mtvsrwz %x0,%1
    xxextractuw %x0,%x1,4"
-  [(set_attr "type" "fpload,fpload,mftgpr,vecexts")
+  [(set_attr "type" "fpload,fpload,mffgpr,vecexts")
    (set_attr "isa" "*,p8v,p8v,p9v")])
 
 (define_insn_and_split "floatunssi<mode>2_lfiwzx"
@@ -7634,7 +7634,7 @@
 	     *,          12,        *,         *")
    (set_attr "type"
 	    "load,       fpload,    fpload,    fpload,    store,     fpstore,
-	     fpstore,    vecfloat,  mffgpr,    *")
+	     fpstore,    vecfloat,  mftgpr,    *")
    (set_attr "isa"
 	    "*,          *,         p9v,       p8v,       *,         *,
 	     p8v,        p8v,       p8v,       *")])
@@ -8711,7 +8711,7 @@
 		   UNSPEC_P8V_MTVSRWZ))]
   "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
   "mtvsrwz %x0,%1"
-  [(set_attr "type" "mftgpr")])
+  [(set_attr "type" "mffgpr")])
 
 (define_insn_and_split "reload_fpr_from_gpr<mode>"
   [(set (match_operand:FMOVE64X 0 "register_operand" "=d")
@@ -8810,7 +8810,7 @@
 		   UNSPEC_P8V_MTVSRD))]
   "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
   "mtvsrd %x0,%1"
-  [(set_attr "type" "mftgpr")])
+  [(set_attr "type" "mffgpr")])
 
 (define_insn_and_split "reload_vsx_from_gprsf"
   [(set (match_operand:SF 0 "register_operand" "=wa")
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 54da54c43dc..3a5cf896da8 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -2885,7 +2885,7 @@
   else
     gcc_unreachable ();
 }
-  [(set_attr "type" "vecperm")])
+  [(set_attr "type" "vecperm,vecmove")])
 
 ;; Combiner patterns to allow creating XXPERMDI's to access either double
 ;; word element in a vector register.
@@ -4440,7 +4440,7 @@
   "@
    xxpermdi %x0,%x1,%x1,0
    mtvsrdd %x0,%1,%1"
-  [(set_attr "type" "vecperm")])
+  [(set_attr "type" "vecperm,vecmove")])
 
 (define_insn "vsx_splat_<mode>_mem"
   [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa")
@@ -4493,7 +4493,7 @@
 	(unspec:V4SF [(match_dup 0)
 		      (const_int 0)] UNSPEC_VSX_XXSPLTW))]
   ""
-  [(set_attr "type" "vecload,vecperm,mftgpr")
+  [(set_attr "type" "vecload,vecperm,vecperm")
    (set_attr "length" "*,8,*")
    (set_attr "isa" "*,p8v,*")])