From: lkcl <lkcl@web>
Date: Sun, 3 Jul 2022 10:25:39 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1394
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b09e4716e54d3cd91f1846e5d5e5f2a8d25e9fcf;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index 69460d8bd..66cb1e370 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -217,12 +217,18 @@ submit RFCs once the External ISA WG RFC Process is in place and,
 in a wholly unsatisfactory manner have to *hope and trust* that
 OPF ISA WG Members are reading this and take it into consideration.
 
+As above sections, it is emphasised strongly that Simple-V in no
+way critically depends on the 100 or so *Scalar* instructions also
+being developed by Libre-SOC. Therefore the Opcode summary below is
+again divided into two: SVP64, then Scalar instructions.
+
+* SVP64 requires 25% of EXT01 (bits 6 and 9 set to 1)
+
 **None of these Draft opcodes are intended for private custom
 secret proprietary usage. They are all intended for entirely
 public, upstream, high-profile mass-volume day-to-day usage at the
 same level as add, popcnt and fld**
 
-* SVP64 requires 25% of EXT01 (bits 6 and 9 set to 1)
 * bitmanip requires two major opcodes (due to 16+ bit immediates)
   those are currently EXT022 and EXT05.
 * brownfield encoding in one of those two major opcodes still