From: lkcl <lkcl@web>
Date: Wed, 8 Sep 2021 13:30:58 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~180
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b0b02244bddcad7fc17204464e37a42aab9a5f25;p=libreriscv.git

---

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 9affbc5ff..ecd2c495e 100644
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -2,7 +2,8 @@
 
 Condition Register Fields are only 4 bits wide: this presents some
 interesting conceptual challenges for SVP64, particularly with respect to element
-width (which is clearly meaningless). Likewise, arithmetic saturation
+width (which is clearly meaningless for a 4-bit
+collation of Conditions, EQ LT GE SO). Likewise, arithmetic saturation
 (an important part of Arithmetic SVP64)
 has no meaning. Additionally, extra modes are required that only make
 sense for Vectorised CR Operations. Consequently an alternative Mode Format is required.