From: Jeff Law Date: Thu, 23 Jul 1998 15:22:17 +0000 (+0000) Subject: * m10300-opc.c: Add autoincrement memory loads/stores. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b0b57954c5b1be38575cd957de51c49fd3b87143;p=binutils-gdb.git * m10300-opc.c: Add autoincrement memory loads/stores. --- diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index f5986218bf6..55bd5611844 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +start-sanitize-am33 +Thu Jul 23 09:21:03 1998 Jeffrey A Law (law@cygnus.com) + + * m10300-opc.c: Add autoincrement memory loads/stores. + +end-sanitize-am33 start-sanitize-r5900 Wed Jul 22 17:05:40 1998 Jeffrey A Law (law@cygnus.com) diff --git a/opcodes/m10300-opc.c b/opcodes/m10300-opc.c index 08a3af66328..2c09ff8c526 100644 --- a/opcodes/m10300-opc.c +++ b/opcodes/m10300-opc.c @@ -342,6 +342,7 @@ const struct mn10300_operand mn10300_operands[] = { #define MEM(ADDR) PAREN, ADDR, PAREN #define MEMINC(ADDR) PAREN, ADDR, PLUS, PAREN +#define MEMINC2(ADDR,INC) PAREN, ADDR, PLUS, INC, PAREN #define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN /* The opcode table. @@ -444,6 +445,19 @@ const struct mn10300_opcode mn10300_opcodes[] = { { "mov", 0xfb9a0000, 0xffff0f00, FMT_D7, AM33, {RM2, MEM2(SD8, SP)}}, { "mov", 0xfd9a0000, 0xffff0f00, FMT_D8, AM33, {RM2, MEM2(SD24, SP)}}, { "mov", 0xfb9e0000, 0xffff000f, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}}, +{ "mov", 0xfb6a0000, 0xffff0000, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), + RN2}}, +{ "mov", 0xfb7a0000, 0xffff0000, FMT_D7, AM33, {RM2, + MEMINC2 (RN0, SIMM8)}}, +{ "mov", 0xfd6a0000, 0xffff0000, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), + RN2}}, +{ "mov", 0xfd7a0000, 0xffff0000, FMT_D8, AM33, {RM2, + MEMINC2 (RN0, IMM24)}}, +{ "mov", 0xfe6a0000, 0xffff0000, FMT_D9, AM33, { + MEMINC2 (RM0, IMM32_HIGH8), + RN2}}, +{ "mov", 0xfe7a0000, 0xffff0000, FMT_D9, AM33, {RN2, + MEMINC2 (RM0, IMM32_HIGH8)}}, /* end-sanitize-am33 */ /* These must come after most of the other move instructions to avoid matching a symbolic name with IMMxx operands. Ugh. */ @@ -465,9 +479,14 @@ const struct mn10300_opcode mn10300_opcodes[] = { { "mov", 0xfc900000, 0xfff30000, FMT_D4, 0, {AM1, MEM2(IMM32, SP)}}, /* These non-promoting variants need to come after all the other memory moves. */ -{ "mov", 0xf8f000, 0xfffc00, FMT_D1, 0, {MEM2(SD8N, AM0), SP}}, -{ "mov", 0xf8f400, 0xfffc00, FMT_D1, 0, {SP, MEM2(SD8N, AN0)}}, -/* start-sanitize-am33 */ +{ "mov", 0xf8f000, 0xfffc00, FMT_D1, AM30, {MEM2(SD8N, AM0), SP}}, +{ "mov", 0xf8f400, 0xfffc00, FMT_D1, AM30, {SP, MEM2(SD8N, AN0)}}, +/* start-sanitize-am33 */ +/* These are the same as the previous non-promoting versions. The am33 + does not have restrictions on the offsets used to load/store the stack + pointer. */ +{ "mov", 0xf8f000, 0xfffc00, FMT_D1, AM33, {MEM2(SD8, AM0), SP}}, +{ "mov", 0xf8f400, 0xfffc00, FMT_D1, AM33, {SP, MEM2(SD8, AN0)}}, /* These must come last so that we favor shorter move instructions for loading immediates into d0-d3/a0-a3. */ { "mov", 0xfb080000, 0xffff0000, FMT_D7, AM33, {SIMM8, RN02}}, @@ -666,6 +685,19 @@ const struct mn10300_opcode mn10300_opcodes[] = { { "movhu", 0xfd5e0000, 0xffff0f00, FMT_D8, AM33, {RM2, MEM(IMM24_MEM)}}, { "movhu", 0xfe5e0000, 0xffff0f00, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}}, +{ "movhu", 0xfbea0000, 0xffff0000, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), + RN2}}, +{ "movhu", 0xfbfa0000, 0xffff0000, FMT_D7, AM33, {RM2, + MEMINC2 (RN0, SIMM8)}}, +{ "movhu", 0xfdea0000, 0xffff0000, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), + RN2}}, +{ "movhu", 0xfdfa0000, 0xffff0000, FMT_D8, AM33, {RM2, + MEMINC2 (RN0, IMM24)}}, +{ "movhu", 0xfeea0000, 0xffff0000, FMT_D9, AM33, { + MEMINC2 (RM0, IMM32_HIGH8), + RN2}}, +{ "movhu", 0xfefa0000, 0xffff0000, FMT_D9, AM33, {RN2, + MEMINC2 (RM0, IMM32_HIGH8)}}, /* end-sanitize-am33 */ { "ext", 0xf2d0, 0xfffc, FMT_D0, 0, {DN0}}, @@ -1439,6 +1471,259 @@ const struct mn10300_opcode mn10300_opcodes[] = { RM2, RN0}}, { "sat16_asl", 0xf7dd0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +/* Ugh. Synthetic instructions. */ +{ "add_and", 0xf7080000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "add_and", 0xf7180000, 0xffff0000, FMT_D10, AM33, {SIMM4_2, RN0, + RM6, RN4}}, +{ "add_dmach", 0xf7090000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "add_dmach", 0xf7190000, 0xffff0000, FMT_D10, AM33, {SIMM4_2, RN0, + RM6, RN4}}, +{ "add_or", 0xf70c0000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "add_or", 0xf71c0000, 0xffff0000, FMT_D10, AM33, {SIMM4_2, RN0, + RM6, RN4}}, +{ "add_sat16", 0xf70d0000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "add_sat16", 0xf71d0000, 0xffff0000, FMT_D10, AM33, {SIMM4_2, RN0, + RM6, RN4}}, +{ "add_swhw", 0xf70b0000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "add_swhw", 0xf71b0000, 0xffff0000, FMT_D10, AM33, {SIMM4_2, RN0, + RM6, RN4}}, +{ "add_xor", 0xf70a0000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "add_xor", 0xf71a0000, 0xffff0000, FMT_D10, AM33, {SIMM4_2, RN0, + RM6, RN4}}, +{ "asl_add", 0xf7c00000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asl_add", 0xf7d00000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + RM6, RN4}}, +{ "asl_add", 0xf7c40000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + SIMM4_6, RN4}}, +{ "asl_add", 0xf7d40000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + SIMM4_6, RN4}}, +{ "asl_and", 0xf7c80000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "asl_and", 0xf7d80000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + RM6, RN4}}, +{ "asl_cmp", 0xf7c10000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asl_cmp", 0xf7d10000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + RM6, RN4, }}, +{ "asl_cmp", 0xf7c50000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + SIMM4_6, RN4}}, +{ "asl_cmp", 0xf7d50000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + SIMM4_6, RN4}}, +{ "asl_dmach", 0xf7c90000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "asl_dmach", 0xf7d90000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + RM6, RN4}}, +{ "asl_mov", 0xf7c30000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asl_mov", 0xf7d30000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + RM6, RN4}}, +{ "asl_mov", 0xf7c70000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + SIMM4_6, RN4}}, +{ "asl_mov", 0xf7d70000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + SIMM4_6, RN4}}, +{ "asl_or", 0xf7cc0000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "asl_or", 0xf7dc0000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + RM6, RN4}}, +{ "asl_sat16", 0xf7cd0000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "asl_sat16", 0xf7dd0000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + RM6, RN4}}, +{ "asl_sub", 0xf7c20000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asl_sub", 0xf7d20000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + RM6, RN4}}, +{ "asl_sub", 0xf7c60000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + SIMM4_6, RN4}}, +{ "asl_sub", 0xf7d60000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + SIMM4_6, RN4}}, +{ "asl_swhw", 0xf7cb0000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "asl_swhw", 0xf7db0000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + RM6, RN4}}, +{ "asl_xor", 0xf7ca0000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "asl_xor", 0xf7da0000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + RM6, RN4}}, +{ "asr_add", 0xf7800000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asr_add", 0xf7900000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + RM6, RN4}}, +{ "asr_add", 0xf7840000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + SIMM4_6, RN4}}, +{ "asr_add", 0xf7940000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + SIMM4_6, RN4}}, +{ "asr_and", 0xf7880000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "asr_and", 0xf7980000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + RM6, RN4}}, +{ "asr_cmp", 0xf7810000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asr_cmp", 0xf7910000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + RM6, RN4, }}, +{ "asr_cmp", 0xf7850000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + SIMM4_6, RN4}}, +{ "asr_cmp", 0xf7950000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + SIMM4_6, RN4}}, +{ "asr_dmach", 0xf7890000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "asr_dmach", 0xf7990000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + RM6, RN4}}, +{ "asr_mov", 0xf7830000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asr_mov", 0xf7930000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + RM6, RN4}}, +{ "asr_mov", 0xf7870000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + SIMM4_6, RN4}}, +{ "asr_mov", 0xf7970000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + SIMM4_6, RN4}}, +{ "asr_or", 0xf78c0000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "asr_or", 0xf79c0000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + RM6, RN4}}, +{ "asr_sat16", 0xf78d0000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "asr_sat16", 0xf79d0000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + RM6, RN4}}, +{ "asr_sub", 0xf7820000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asr_sub", 0xf7920000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + RM6, RN4}}, +{ "asr_sub", 0xf7860000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + SIMM4_6, RN4}}, +{ "asr_sub", 0xf7960000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + SIMM4_6, RN4}}, +{ "asr_swhw", 0xf78b0000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "asr_swhw", 0xf79b0000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + RM6, RN4}}, +{ "asr_xor", 0xf78a0000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "asr_xor", 0xf79a0000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + RM6, RN4}}, +{ "cmp_and", 0xf7480000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "cmp_and", 0xf7580000, 0xffff0000, FMT_D10, AM33, {SIMM4_2, RN0, + RM6, RN4}}, +{ "cmp_dmach", 0xf7490000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "cmp_dmach", 0xf7590000, 0xffff0000, FMT_D10, AM33, {SIMM4_2, RN0, + RM6, RN4}}, +{ "cmp_or", 0xf74c0000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "cmp_or", 0xf75c0000, 0xffff0000, FMT_D10, AM33, {SIMM4_2, RN0, + RM6, RN4}}, +{ "cmp_sat16", 0xf74d0000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "cmp_sat16", 0xf75d0000, 0xffff0000, FMT_D10, AM33, {SIMM4_2, RN0, + RM6, RN4}}, +{ "cmp_swhw", 0xf74b0000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "cmp_swhw", 0xf75b0000, 0xffff0000, FMT_D10, AM33, {SIMM4_2, RN0, + RM6, RN4}}, +{ "cmp_xor", 0xf74a0000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "cmp_xor", 0xf75a0000, 0xffff0000, FMT_D10, AM33, {SIMM4_2, RN0, + RM6, RN4}}, +{ "lsr_add", 0xf7a00000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "lsr_add", 0xf7900000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + RM6, RN4}}, +{ "lsr_add", 0xf7a40000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + SIMM4_6, RN4}}, +{ "lsr_add", 0xf7b40000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + SIMM4_6, RN4}}, +{ "lsr_and", 0xf7a80000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "lsr_and", 0xf7b80000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + RM6, RN4}}, +{ "lsr_cmp", 0xf7a10000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "lsr_cmp", 0xf7b10000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + RM6, RN4, }}, +{ "lsr_cmp", 0xf7a50000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + SIMM4_6, RN4}}, +{ "lsr_cmp", 0xf7b50000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + SIMM4_6, RN4}}, +{ "lsr_dmach", 0xf7a90000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "lsr_dmach", 0xf7b90000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + RM6, RN4}}, +{ "lsr_mov", 0xf7a30000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "lsr_mov", 0xf7b30000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + RM6, RN4}}, +{ "lsr_mov", 0xf7a70000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + SIMM4_6, RN4}}, +{ "lsr_mov", 0xf7b70000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + SIMM4_6, RN4}}, +{ "lsr_or", 0xf7ac0000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "lsr_or", 0xf7bc0000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + RM6, RN4}}, +{ "lsr_sat16", 0xf7ad0000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "lsr_sat16", 0xf7bd0000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + RM6, RN4}}, +{ "lsr_sub", 0xf7a20000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "lsr_sub", 0xf7b20000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + RM6, RN4}}, +{ "lsr_sub", 0xf7a60000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + SIMM4_6, RN4}}, +{ "lsr_sub", 0xf7b60000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + SIMM4_6, RN4}}, +{ "lsr_swhw", 0xf7ab0000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "lsr_swhw", 0xf7bb0000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + RM6, RN4}}, +{ "lsr_xor", 0xf7aa0000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "lsr_xor", 0xf7ba0000, 0xffff0000, FMT_D10, AM33, {IMM4_2, RN0, + RM6, RN4}}, +{ "mov_and", 0xf7680000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "mov_and", 0xf7780000, 0xffff0000, FMT_D10, AM33, {SIMM4_2, RN0, + RM6, RN4}}, +{ "mov_dmach", 0xf7690000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "mov_dmach", 0xf7790000, 0xffff0000, FMT_D10, AM33, {SIMM4_2, RN0, + RM6, RN4}}, +{ "mov_or", 0xf76c0000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "mov_or", 0xf77c0000, 0xffff0000, FMT_D10, AM33, {SIMM4_2, RN0, + RM6, RN4}}, +{ "mov_sat16", 0xf76d0000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "mov_sat16", 0xf77d0000, 0xffff0000, FMT_D10, AM33, {SIMM4_2, RN0, + RM6, RN4}}, +{ "mov_swhw", 0xf76b0000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "mov_swhw", 0xf77b0000, 0xffff0000, FMT_D10, AM33, {SIMM4_2, RN0, + RM6, RN4}}, +{ "mov_xor", 0xf76a0000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "mov_xor", 0xf77a0000, 0xffff0000, FMT_D10, AM33, {SIMM4_2, RN0, + RM6, RN4}}, +{ "sub_and", 0xf7280000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "sub_and", 0xf7380000, 0xffff0000, FMT_D10, AM33, {SIMM4_2, RN0, + RM6, RN4}}, +{ "sub_dmach", 0xf7290000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "sub_dmach", 0xf7390000, 0xffff0000, FMT_D10, AM33, {SIMM4_2, RN0, + RM6, RN4}}, +{ "sub_or", 0xf72c0000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "sub_or", 0xf73c0000, 0xffff0000, FMT_D10, AM33, {SIMM4_2, RN0, + RM6, RN4}}, +{ "sub_sat16", 0xf72d0000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "sub_sat16", 0xf73d0000, 0xffff0000, FMT_D10, AM33, {SIMM4_2, RN0, + RM6, RN4}}, +{ "sub_swhw", 0xf72b0000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "sub_swhw", 0xf73b0000, 0xffff0000, FMT_D10, AM33, {SIMM4_2, RN0, + RM6, RN4}}, +{ "sub_xor", 0xf72a0000, 0xffff0000, FMT_D10, AM33, {RM2, RN0, + RM6, RN4}}, +{ "sub_xor", 0xf73a0000, 0xffff0000, FMT_D10, AM33, {SIMM4_2, RN0, + RM6, RN4}}, /* end-sanitize-am33 */ { 0, 0, 0, 0, 0, {0}},