From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 18 Aug 2020 11:39:51 +0000 (+0100)
Subject: fix spr state test
X-Git-Tag: semi_working_ecp5~298
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b0b640d411b52c2c66eb65f853ea45c14f21fbff;p=soc.git

fix spr state test
---

diff --git a/src/soc/fu/spr/test/test_pipe_caller.py b/src/soc/fu/spr/test/test_pipe_caller.py
index b3452ca8..a824e8ae 100644
--- a/src/soc/fu/spr/test/test_pipe_caller.py
+++ b/src/soc/fu/spr/test/test_pipe_caller.py
@@ -200,8 +200,8 @@ class TestRunner(unittest.TestCase):
 
                     # ask the decoder to decode this binary data (endian'd)
                     yield pdecode2.dec.bigendian.eq(bigendian)  # little / big?
-                    yield pdecode2.msr.eq(msr)  # set MSR in pdecode2
-                    yield pdecode2.cia.eq(pc)  # set PC in pdecode2
+                    yield pdecode2.state.msr.eq(msr)  # set MSR in pdecode2
+                    yield pdecode2.state.pc.eq(pc)  # set PC in pdecode2
                     yield instruction.eq(ins)          # raw binary instr.
                     yield Settle()