From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 4 Apr 2015 16:06:52 +0000 (+0200)
Subject: Added "init" attribute support to verilog backend
X-Git-Tag: yosys-0.6~363
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b0c0ede879341c0beeae4a9a5e8578da12f3b3f1;p=yosys.git

Added "init" attribute support to verilog backend
---

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index ba57e8814..0d667c638 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -299,6 +299,11 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
 		f << stringf("%s" "reg%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());
 	else if (!wire->port_input && !wire->port_output)
 		f << stringf("%s" "wire%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());
+	if (wire->attributes.count("\\init")) {
+		f << stringf("%s" "initial %s = ", indent.c_str(), id(wire->name).c_str());
+		dump_const(f, wire->attributes.at("\\init"));
+		f << stringf(";\n");
+	}
 #endif
 }