From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Thu, 8 Dec 2011 22:04:20 +0000 (+0100)
Subject: verilog: handle default in case statements
X-Git-Tag: 24jan2021_ls180~2099^2~1161
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b0c5b74c2284d1325d1dab1bed7492e9e03fb74c;p=litex.git

verilog: handle default in case statements
---

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index 05b231cc..c403e897 100644
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -65,6 +65,10 @@ def _printnode(ns, level, comb, node):
 			r += "\t"*(level + 1) + _printexpr(ns, case[0]) + ": begin\n"
 			r += _printnode(ns, level + 2, comb, case[1])
 			r += "\t"*(level + 1) + "end\n"
+		if node.default.l:
+			r += "\t"*(level + 1) + "default: begin\n"
+			r += _printnode(ns, level + 2, comb, node.default)
+			r += "\t"*(level + 1) + "end\n"
 		r += "\t"*level + "endcase\n"
 		return r
 	else: