From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 26 Nov 2018 04:45:05 +0000 (+0000)
Subject: move stuff to MInfo
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b0d897238492346241e62d168ac7ca57ea3e14b1;p=rv32.git

move stuff to MInfo
---

diff --git a/cpu.py b/cpu.py
index 8e9352c..9d50e59 100644
--- a/cpu.py
+++ b/cpu.py
@@ -292,6 +292,31 @@ class CSR:
 
         return Case(self.number, c)
 
+    def evaluate_csr_funct3_op(self, funct3, previous_value, written_value):
+        c = { "default": Constant(0, 32)}
+        for f in [F3.csrrw, F3.csrrwi]: c[f] = written_value
+        for f in [F3.csrrs, F3.csrrsi]: c[f] = written_value | previous_value
+        for f in [F3.csrrc, F3.csrrci]: c[f] = ~written_value & previous_value
+        return Case(funct3, c)
+
+
+class MInfo:
+    def __init__(self, comb):
+        self.comb = comb
+        # TODO
+        self.cycle_counter   = Signal(64); # TODO: implement cycle_counter
+        self.time_counter    = Signal(64); # TODO: implement time_counter
+        self.instret_counter = Signal(64); # TODO: implement instret_counter
+
+        self.mvendorid = Signal(32)
+        self.marchid = Signal(32)
+        self.mimpid = Signal(32)
+        self.mhartid = Signal(32)
+        self.comb += self.mvendorid.eq(Constant(0, 32))
+        self.comb += self.marchid.eq(Constant(0, 32))
+        self.comb += self.mimpid.eq(Constant(0, 32))
+        self.comb += self.mhartid.eq(Constant(0, 32))
+
 
 class CPU(Module):
     """
@@ -324,13 +349,6 @@ class CPU(Module):
                   self.registers[register_number].eq(value)
                )
 
-    def evaluate_csr_funct3_op(self, funct3, previous_value, written_value):
-        c = { "default": Constant(0, 32)}
-        for f in [F3.csrrw, F3.csrrwi]: c[f] = written_value
-        for f in [F3.csrrs, F3.csrrsi]: c[f] = written_value | previous_value
-        for f in [F3.csrrc, F3.csrrci]: c[f] = ~written_value & previous_value
-        return Case(funct3, c)
-
     def handle_trap(self, m, ms, ft, dc, load_store_misaligned):
         s = [ms.mpie.eq(ms.mie),
              ms.mie.eq(0),
@@ -379,21 +397,23 @@ class CPU(Module):
         s.append(i)
         return s
 
-    def main_block(self, csr, mi, m, mstatus, ft, dc, load_store_misaligned,
+    def main_block(self, minfo, csr, mi, m, mstatus, ft, dc,
+                         load_store_misaligned,
                          loaded_value, alu_result,
                          lui_auipc_result):
         c = {}
         c[FOS.empty] = []
         c[FOS.trap] = self.handle_trap(m, mstatus, ft, dc,
                                        load_store_misaligned)
-        c[FOS.valid] = self.handle_valid(csr, mi, m, mstatus, ft, dc,
+        c[FOS.valid] = self.handle_valid(minfo, csr, mi, m, mstatus, ft, dc,
                                        load_store_misaligned,
                                        loaded_value,
                                        alu_result,
                                        lui_auipc_result)
         return Case(ft.output_state, c)
 
-    def handle_valid(self, csr, mi, m, mstatus, ft, dc, load_store_misaligned,
+    def handle_valid(self, minfo, csr, mi, m, mstatus, ft, dc,
+                           load_store_misaligned,
                            loaded_value, alu_result,
                            lui_auipc_result):
         # fetch action ack trap
@@ -425,7 +445,7 @@ class CPU(Module):
               )
 
         i = i.Elif((dc.act & DA.csr) != 0,
-                self.handle_csr(dc, csr)
+                self.handle_csr(minfo, mstatus, dc, csr)
               )
 
         # fence, store, branch
@@ -436,11 +456,14 @@ class CPU(Module):
 
         return i
 
-    def handle_csr(self, dc, csr):
-        return []
+    def handle_csr(self, minfo, mstatus, dc, csr):
+        csr_output_value = Signal()
+        csr_written_value = Signal()
+        c = {}
+
+        return Case(csr.number, c)
 
         """
-            else if((decode_action & `decode_action_csr) != 0) begin:csr
                 reg [31:0] csr_output_value;
                 reg [31:0] csr_written_value;
                 csr_output_value = 32'hXXXXXXXX;
@@ -785,18 +808,7 @@ class CPU(Module):
         m = M(self.comb, self.sync)
         mstatus = MStatus(self.comb, self.sync)
         mie = MIE(self.comb, self.sync)
-
         misa = Misa(self.comb, self.sync)
-
-        mvendorid = Signal(32)
-        marchid = Signal(32)
-        mimpid = Signal(32)
-        mhartid = Signal(32)
-        self.comb += mvendorid.eq(Constant(0, 32))
-        self.comb += marchid.eq(Constant(0, 32))
-        self.comb += mimpid.eq(Constant(0, 32))
-        self.comb += mhartid.eq(Constant(0, 32))
-
         mip = MIP(self.comb, self.sync)
 
         # CSR decoding
@@ -806,13 +818,10 @@ class CPU(Module):
                                  branch_taken, misaligned_jump_target,
                                  csr.op_is_valid)
 
-        # TODO
-        cycle_counter   = Signal(64); # TODO: implement cycle_counter
-        time_counter    = Signal(64); # TODO: implement time_counter
-        instret_counter = Signal(64); # TODO: implement instret_counter
+        minfo = MInfo(self.comb)
 
         self.sync += If(~self.reset,
-                        self.main_block(csr, mi, m, mstatus, ft, dc,
+                        self.main_block(minfo, csr, mi, m, mstatus, ft, dc,
                                         load_store_misaligned,
                                         loaded_value,
                                        alu_result,