From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 22 Dec 2021 00:49:07 +0000 (+0000)
Subject: clear instruction fault on exception WAIT_MMU ACK in LoadStore1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b0f16cf896c5888893ec3326fbfa4a4e584552dd;p=soc.git

clear instruction fault on exception WAIT_MMU ACK in LoadStore1
---

diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py
index 8ad751e7..eb452dbf 100644
--- a/src/soc/fu/ldst/loadstore.py
+++ b/src/soc/fu/ldst/loadstore.py
@@ -255,6 +255,7 @@ class LoadStore1(PortInterfaceBase):
                         # XXX there is no architected bit for this
                         # (probably should be a machine check in fact)
                         sync += self.dsisr[63 - 35].eq(d_in.cache_paradox)
+                        sync += self.r_instr_fault.eq(0)
 
                     with m.Else():
                         # Look up the translation for TLB miss