From: Jędrzej Boczar <yendreij@gmail.com>
Date: Fri, 17 Apr 2020 12:52:53 +0000 (+0200)
Subject: litex_sim: add option to create SDRAM module from SPD data
X-Git-Tag: 24jan2021_ls180~440^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b0f8ee987667e4517574ff590f5baff336bfb9d7;p=litex.git

litex_sim: add option to create SDRAM module from SPD data
---

diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index 8ac544fc..7a526f83 100755
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -166,6 +166,7 @@ class SimSoC(SoCSDRAM):
         sdram_module          = "MT48LC16M16",
         sdram_init            = [],
         sdram_data_width      = 32,
+        sdram_spd_data        = None,
         sdram_verbosity       = 0,
         **kwargs):
         platform     = Platform()
@@ -182,9 +183,12 @@ class SimSoC(SoCSDRAM):
         # SDRAM ------------------------------------------------------------------------------------
         if with_sdram:
             sdram_clk_freq   = int(100e6) # FIXME: use 100MHz timings
-            sdram_module_cls = getattr(litedram_modules, sdram_module)
-            sdram_rate       = "1:{}".format(sdram_module_nphases[sdram_module_cls.memtype])
-            sdram_module     = sdram_module_cls(sdram_clk_freq, sdram_rate)
+            if sdram_spd_data is None:
+                sdram_module_cls = getattr(litedram_modules, sdram_module)
+                sdram_rate       = "1:{}".format(sdram_module_nphases[sdram_module_cls.memtype])
+                sdram_module     = sdram_module_cls(sdram_clk_freq, sdram_rate)
+            else:
+                sdram_module = litedram_modules.SDRAMModule.from_spd_data(sdram_spd_data, sdram_clk_freq)
             phy_settings     = get_sdram_phy_settings(
                 memtype    = sdram_module.memtype,
                 data_width = sdram_data_width,
@@ -285,6 +289,7 @@ def main():
     parser.add_argument("--sdram-module",         default="MT48LC16M16",   help="Select SDRAM chip")
     parser.add_argument("--sdram-data-width",     default=32,              help="Set SDRAM chip data width")
     parser.add_argument("--sdram-init",           default=None,            help="SDRAM init file")
+    parser.add_argument("--sdram-from-spd-data",  default=None,            help="Generate SDRAM module based on SPD data from file")
     parser.add_argument("--sdram-verbosity",      default=0,               help="Set SDRAM checker verbosity")
     parser.add_argument("--with-ethernet",        action="store_true",     help="Enable Ethernet support")
     parser.add_argument("--with-etherbone",       action="store_true",     help="Enable Etherbone support")
@@ -323,6 +328,9 @@ def main():
         soc_kwargs["sdram_module"]             = args.sdram_module
         soc_kwargs["sdram_data_width"]         = int(args.sdram_data_width)
         soc_kwargs["sdram_verbosity"]          = int(args.sdram_verbosity)
+        if args.sdram_from_spd_data:
+            with open(args.sdram_from_spd_data, "rb") as f:
+                soc_kwargs["sdram_spd_data"] = [int(b) for b in f.read()]
 
     if args.with_ethernet or args.with_etherbone:
         sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": args.remote_ip})