From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 4 Apr 2020 20:53:03 +0000 (+0100)
Subject: import EXTS which over-extends to 256 bits
X-Git-Tag: div_pipeline~1512
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b0f94a3f110435ac8c4f5e8a25998b2977b97545;p=soc.git

import EXTS which over-extends to 256 bits
---

diff --git a/src/soc/decoder/helpers.py b/src/soc/decoder/helpers.py
index 941bcbc8..98b3e672 100644
--- a/src/soc/decoder/helpers.py
+++ b/src/soc/decoder/helpers.py
@@ -7,17 +7,26 @@ def exts(value, bits):
     return (value & (sign - 1)) - (value & sign)
 
 
+def EXTS(value):
+    """ extends sign bit out from current MSB to all 256 bits
+    """
+    assert isinstance(value, SelectableInt)
+    return SelectableInt(exts(value.value, value.bits) & ((1 << 256)-1), 256)
+
 def EXTS64(value):
-    if isinstance(value, SelectableInt):
-        value = value.value
-    return SelectableInt(exts(value, 32) & ((1 << 64)-1), 64)
+    """ extends sign bit out from current MSB to 64 bits
+    """
+    assert isinstance(value, SelectableInt)
+    return SelectableInt(exts(value.value, value.bits) & ((1 << 64)-1), 64)
 
 
+# XXX should this explicitly extend from 32 to 64?
 def EXTZ64(value):
     if isinstance(value, SelectableInt):
         value = value.value
     return SelectableInt(value & ((1<<32)-1), 64)
 
+
 def rotl(value, bits, wordlen):
     mask = (1 << wordlen) - 1
     bits = bits & (wordlen - 1)
diff --git a/src/soc/decoder/pseudo/pywriter.py b/src/soc/decoder/pseudo/pywriter.py
index 049a1f39..40d10e8c 100644
--- a/src/soc/decoder/pseudo/pywriter.py
+++ b/src/soc/decoder/pseudo/pywriter.py
@@ -16,7 +16,7 @@ header = """\
 # auto-generated by pywriter.py, do not edit or commit
 
 from soc.decoder.isa.caller import ISACaller, inject
-from soc.decoder.helpers import (EXTS64, EXTZ64, ROTL64, ROTL32, MASK,)
+from soc.decoder.helpers import (EXTS, EXTS64, EXTZ64, ROTL64, ROTL32, MASK,)
 from soc.decoder.selectable_int import SelectableInt
 from soc.decoder.selectable_int import selectconcat as concat
 from soc.decoder.orderedset import OrderedSet
@@ -72,8 +72,9 @@ class PyISAWriter(ISA):
 
 if __name__ == '__main__':
     isa = PyISAWriter()
-    isa.write_pysource('fixedlogical')
+    isa.write_pysource('branch')
     exit(0)
+    isa.write_pysource('fixedlogical')
     isa.write_pysource('fixedstore')
     isa.write_pysource('fixedload')
     isa.write_pysource('comparefixed')