From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Mon, 8 Jun 2020 14:14:50 +0000 (+0200)
Subject: Fix bugs in ECP5DDRPHY instanciation
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b10105f41cdd4247316e40780e2d797f082b02b1;p=gram.git

Fix bugs in ECP5DDRPHY instanciation
---

diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py
index e228f4d..243e613 100644
--- a/gram/phy/ecp5ddrphy.py
+++ b/gram/phy/ecp5ddrphy.py
@@ -121,28 +121,16 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
         databits = len(self.pads.dq.oe)
         self.dfi = Interface(addressbits, bankbits, nranks, 4*databits, 4)
 
-    def elaborate(self, platform):
-        m = Module()
-
+        # PHY settings -----------------------------------------------------------------------------
         tck = 2/(2*2*self._sys_clk_freq)
         nphases = 2
         databits = len(self.pads.dq.oe)
         nranks = 1 if not hasattr(self.pads, "cs_n") else len(self.pads.cs_n)
         addressbits = len(self.pads.a.o)
         bankbits = len(self.pads.ba.o)
-
-        # Init -------------------------------------------------------------------------------------
-        m.submodules.init = DomainRenamer("init")(ECP5DDRPHYInit("sys2x"))
-
-        # Parameters -------------------------------------------------------------------------------
         cl, cwl         = get_cl_cw("DDR3", tck)
         cl_sys_latency  = get_sys_latency(nphases, cl)
         cwl_sys_latency = get_sys_latency(nphases, cwl)
-
-        # Observation
-        self.datavalid = Signal(databits//8)
-
-        # PHY settings -----------------------------------------------------------------------------
         rdcmdphase, rdphase = get_sys_phases(nphases, cl_sys_latency, cl)
         wrcmdphase, wrphase = get_sys_phases(nphases, cwl_sys_latency, cwl)
         self.settings = PhySettings(
@@ -162,11 +150,30 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
             write_latency = cwl_sys_latency
         )
 
+    def elaborate(self, platform):
+        m = Module()
+
+        tck = 2/(2*2*self._sys_clk_freq)
+        nphases = 2
+        databits = len(self.pads.dq.oe)
+        nranks = 1 if not hasattr(self.pads, "cs_n") else len(self.pads.cs_n)
+        addressbits = len(self.pads.a.o)
+        bankbits = len(self.pads.ba.o)
+
+        # Init -------------------------------------------------------------------------------------
+        m.submodules.init = DomainRenamer("init")(ECP5DDRPHYInit("sys2x"))
+
+        # Parameters -------------------------------------------------------------------------------
+        cl, cwl         = get_cl_cw("DDR3", tck)
+        cl_sys_latency  = get_sys_latency(nphases, cl)
+        cwl_sys_latency = get_sys_latency(nphases, cwl)
+
+        # Observation
+        self.datavalid = Signal(databits//8)
+
         # DFI Interface ----------------------------------------------------------------------------
         dfi = self.dfi
 
-        # # #
-
         bl8_chunk   = Signal()
         rddata_en = Signal(self.settings.read_latency)