From: Robert Ou <rqou@robertou.com>
Date: Mon, 26 Jun 2017 06:56:16 +0000 (-0700)
Subject: coolrunner2: Add a few more primitives
X-Git-Tag: yosys-0.8~402^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b102c0e2544d3bba8f8982db9dfb4974a0170368;p=yosys.git

coolrunner2: Add a few more primitives

These cannot be inferred yet, but add them to cells_sim.v for now
---

diff --git a/techlibs/coolrunner2/cells_sim.v b/techlibs/coolrunner2/cells_sim.v
index 90eb4eb16..e08ee5f9b 100644
--- a/techlibs/coolrunner2/cells_sim.v
+++ b/techlibs/coolrunner2/cells_sim.v
@@ -134,3 +134,113 @@ module LDCP_N (G, PRE, CLR, D, Q);
             Q <= 1;
     end
 endmodule
+
+module BUFG(I, O);
+    input I;
+    output O;
+
+    assign O = I;
+endmodule
+
+module BUFGSR(I, O);
+    input I;
+    output O;
+
+    assign O = I;
+endmodule
+
+module BUFGTS(I, O);
+    input I;
+    output O;
+
+    assign O = I;
+endmodule
+
+module FDDCP (C, PRE, CLR, D, Q);
+    parameter INIT = 0;
+
+    input C, PRE, CLR, D;
+    output reg Q;
+
+    initial begin
+        Q <= INIT;
+    end
+
+    always @(posedge C, negedge C, posedge PRE, posedge CLR) begin
+        if (CLR == 1)
+            Q <= 0;
+        else if (PRE == 1)
+            Q <= 1;
+        else
+            Q <= D;
+    end
+endmodule
+
+module FTCP (C, PRE, CLR, T, Q);
+    parameter INIT = 0;
+
+    input C, PRE, CLR, T;
+    output wire Q;
+    reg Q_;
+
+    initial begin
+        Q_ <= INIT;
+    end
+
+    always @(posedge C, posedge PRE, posedge CLR) begin
+        if (CLR == 1)
+            Q_ <= 0;
+        else if (PRE == 1)
+            Q_ <= 1;
+        else if (T == 1)
+            Q_ <= ~Q_;
+    end
+
+    assign Q = Q_;
+endmodule
+
+module FTCP_N (C, PRE, CLR, T, Q);
+    parameter INIT = 0;
+
+    input C, PRE, CLR, T;
+    output wire Q;
+    reg Q_;
+
+    initial begin
+        Q_ <= INIT;
+    end
+
+    always @(negedge C, posedge PRE, posedge CLR) begin
+        if (CLR == 1)
+            Q_ <= 0;
+        else if (PRE == 1)
+            Q_ <= 1;
+        else if (T == 1)
+            Q_ <= ~Q_;
+    end
+
+    assign Q = Q_;
+endmodule
+
+module FTDCP (C, PRE, CLR, T, Q);
+    parameter INIT = 0;
+
+    input C, PRE, CLR, T;
+    output wire Q;
+    reg Q_;
+
+    initial begin
+        Q_ <= INIT;
+    end
+
+    always @(posedge C, negedge C, posedge PRE, posedge CLR) begin
+        if (CLR == 1)
+            Q_ <= 0;
+        else if (PRE == 1)
+            Q_ <= 1;
+        else if (T == 1)
+            Q_ <= ~Q_;
+    end
+
+    assign Q = Q_;
+endmodule