From: lkcl <lkcl@web>
Date: Sun, 3 Oct 2021 11:54:15 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~3734
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b10fe26a346b808cb3c08687701beebd878685c2;p=libreriscv.git

---

diff --git a/3d_gpu/architecture/dynamic_simd.mdwn b/3d_gpu/architecture/dynamic_simd.mdwn
index fa0ba58dd..3efdba7ca 100644
--- a/3d_gpu/architecture/dynamic_simd.mdwn
+++ b/3d_gpu/architecture/dynamic_simd.mdwn
@@ -325,7 +325,7 @@ has two different inter-related abstraction levels.
   to use macro substitution or crude compilers to autogenerate the dynamic
   SIMD from VHDL / Verilog templates, why not do exactly the same thing.
   Design a SIMD HDL language, write python in that, and have it output
-  nmigen HDL.
+  python source code with nmigen HDL.
 
 All of these ideas, unfortunately, are extremely costly in many different ways: