From: Tim 'mithro' Ansell <me@mith.ro>
Date: Mon, 8 Oct 2018 23:52:12 +0000 (-0700)
Subject: xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.
X-Git-Tag: yosys-0.9~441^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b111ea12286b45e51fc453e3f4d7ac906e1a9f7c;p=yosys.git

xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.

Then if targeting vpr map all the Xilinx specific LUTs back into generic
Yosys LUTs.
---

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 590fe61d2..b27c08529 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -235,10 +235,9 @@ struct SynthXilinxPass : public Pass
 
 		if (check_label(active, run_from, run_to, "map_cells"))
 		{
+			Pass::call(design, "techmap -map +/xilinx/cells_map.v");
 			if (vpr)
-			    Pass::call(design, "techmap -D NO_LUT -map +/xilinx/cells_map.v");
-			else
-			    Pass::call(design, "techmap -map +/xilinx/cells_map.v");
+			    Pass::call(design, "techmap -map +/xilinx/lut2lut.v");
 			Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT");
 			Pass::call(design, "clean");
 		}