From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 14 Feb 2019 08:32:13 +0000 (+0000)
Subject: reformat / indent add_0 stage
X-Git-Tag: ls180-24jan2020~2024
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b122b5740d630b5348ab2c63c911e840b6053807;p=ieee754fpu.git

reformat / indent add_0 stage
---

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index 119b1356..601b56e9 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -184,21 +184,25 @@ class FPADD:
                     with m.Else():
                         m.d.sync += b_m[26].eq(1) # set highest mantissa bit
 
-            with m.State("add_0"):
-              m.next = "add_1"
-              m.d.sync += z_e.eq(a_e)
-              with m.If(a_s == b_s):
-                m.d.sync += [
-                tot.eq(a_m + b_m),
-                z_s.eq(a_s)]
-              with m.Else(a_m >= b_m):
-                m.d.sync += [
-                tot.eq(a_m - b_m),
-                z_s.eq(a_s)]
-              with m.Else():
-                m.sync += [
-                tot.eq(b_m - a_m),
-                z_s.eq(b_s)]
+                # First stage of add
+                with m.State("add_0"):
+                    m.next = "add_1"
+                    m.d.sync += z_e.eq(a_e)
+                    with m.If(a_s == b_s):
+                        m.d.sync += [
+                            tot.eq(a_m + b_m),
+                            z_s.eq(a_s)
+                        ]
+                    with m.Else(a_m >= b_m):
+                        m.d.sync += [
+                            tot.eq(a_m - b_m),
+                            z_s.eq(a_s)
+                        ]
+                    with m.Else():
+                        m.sync += [
+                            tot.eq(b_m - a_m),
+                            z_s.eq(b_s)
+                    ]
         return m
 
 """