From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 24 May 2020 19:01:56 +0000 (+0100)
Subject: add links for trap main stage
X-Git-Tag: div_pipeline~870
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b122e4cd357247a5c3157ab77d67211b1116ed72;p=soc.git

add links for trap main stage
---

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index 4efbff00..2d42c153 100644
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -1,6 +1,8 @@
 """Trap Pipeline
 
 * https://bugs.libre-soc.org/show_bug.cgi?id=325
+* https://bugs.libre-soc.org/show_bug.cgi?id=344
+* https://libre-soc.org/openpower/isa/fixedtrap/
 """
 
 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, signed)