From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 22 Mar 2018 05:46:58 +0000 (+0000)
Subject: Revert "more alteration of wire_defs to make auto-generation easier"
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b126af27bccafdd023f99bd567560c51dee534a6;p=pinmux.git

Revert "more alteration of wire_defs to make auto-generation easier"

This reverts commit c5846936454d7d0e45aa39a4f16064797908e348.

(actually not easier)
---

diff --git a/src/wire_def.py b/src/wire_def.py
index f14fe32..9e6b90d 100644
--- a/src/wire_def.py
+++ b/src/wire_def.py
@@ -7,6 +7,7 @@ generic_io = '''
 '''
 uartwires = '''
       Wire#(Bit#(1)) wruart{0}_rx<-mkDWire(0);
+      Wire#(Bit#(1)) wruart{0}_tx<-mkDWire(0);
       GenericIOType uart{0}_rx_io=GenericIOType{{
                  outputval:0,
                  output_en:0,
@@ -17,7 +18,6 @@ uartwires = '''
                  drivestrength:0,
                  opendrain_en:0
       }};
-      Wire#(Bit#(1)) wruart{0}_tx<-mkDWire(0);
       GenericIOType uart{0}_tx_io=GenericIOType{{
                  outputval:wruart{0}_tx,
                  output_en:1,
@@ -31,6 +31,9 @@ uartwires = '''
 '''
 spiwires = '''
       Wire#(Bit#(1)) wrspi{0}_sclk<-mkDWire(0);
+      Wire#(Bit#(1)) wrspi{0}_mosi<-mkDWire(0);
+      Wire#(Bit#(1)) wrspi{0}_ss<-mkDWire(0);
+      Wire#(Bit#(1)) wrspi{0}_miso<-mkDWire(0);
       GenericIOType spi{0}_sclk_io = GenericIOType{{
                  outputval:wrspi{0}_sclk,
                  output_en:1,
@@ -41,7 +44,6 @@ spiwires = '''
                  drivestrength:0,
                  opendrain_en:0
       }};
-      Wire#(Bit#(1)) wrspi{0}_mosi<-mkDWire(0);
       GenericIOType spi{0}_mosi_io = GenericIOType{{
                  outputval:wrspi{0}_mosi,
                  output_en:1,
@@ -52,7 +54,6 @@ spiwires = '''
                  drivestrength:0,
                  opendrain_en:0
       }};
-      Wire#(Bit#(1)) wrspi{0}_ss<-mkDWire(0);
       GenericIOType spi{0}_ss_io = GenericIOType{{
                  outputval:wrspi{0}_ss,
                  output_en:1,
@@ -63,7 +64,6 @@ spiwires = '''
                  drivestrength:0,
                  opendrain_en:0
       }};
-      Wire#(Bit#(1)) wrspi{0}_miso<-mkDWire(0);
       GenericIOType spi{0}_miso_io = GenericIOType{{
                  outputval:0,
                  output_en:0,
@@ -80,6 +80,9 @@ twiwires = '''
       Wire#(Bit#(1)) wrtwi{0}_sda_out<-mkDWire(0);
       Wire#(Bit#(1)) wrtwi{0}_sda_outen<-mkDWire(0);
       Wire#(Bit#(1)) wrtwi{0}_sda_in<-mkDWire(0);
+      Wire#(Bit#(1)) wrtwi{0}_scl_out<-mkDWire(0);
+      Wire#(Bit#(1)) wrtwi{0}_scl_outen<-mkDWire(0);
+      Wire#(Bit#(1)) wrtwi{0}_scl_in<-mkDWire(0);
       GenericIOType  twi{0}_sda_io = GenericIOType{{
                  outputval:wrtwi{0}_sda_out,
                  output_en:wrtwi{0}_sda_outen,
@@ -90,9 +93,6 @@ twiwires = '''
                  drivestrength:0,
                  opendrain_en:0
       }};
-      Wire#(Bit#(1)) wrtwi{0}_scl_out<-mkDWire(0);
-      Wire#(Bit#(1)) wrtwi{0}_scl_outen<-mkDWire(0);
-      Wire#(Bit#(1)) wrtwi{0}_scl_in<-mkDWire(0);
       GenericIOType  twi{0}_scl_io = GenericIOType{{
                  outputval:wrtwi{0}_scl_out,
                  output_en:wrtwi{0}_scl_outen,
@@ -107,6 +107,19 @@ twiwires = '''
 
 sdwires = '''
       Wire#(Bit#(1)) wrsd{0}_clk<-mkDWire(0);
+      Wire#(Bit#(1)) wrsd{0}_cmd<-mkDWire(0);
+      Wire#(Bit#(1)) wrsd{0}_d0_out<-mkDWire(0);
+      Wire#(Bit#(1)) wrsd{0}_d0_outen<-mkDWire(0);
+      Wire#(Bit#(1)) wrsd{0}_d0_in<-mkDWire(0);
+      Wire#(Bit#(1)) wrsd{0}_d1_out<-mkDWire(0);
+      Wire#(Bit#(1)) wrsd{0}_d1_outen<-mkDWire(0);
+      Wire#(Bit#(1)) wrsd{0}_d1_in<-mkDWire(0);
+      Wire#(Bit#(1)) wrsd{0}_d2_out<-mkDWire(0);
+      Wire#(Bit#(1)) wrsd{0}_d2_outen<-mkDWire(0);
+      Wire#(Bit#(1)) wrsd{0}_d2_in<-mkDWire(0);
+      Wire#(Bit#(1)) wrsd{0}_d3_out<-mkDWire(0);
+      Wire#(Bit#(1)) wrsd{0}_d3_outen<-mkDWire(0);
+      Wire#(Bit#(1)) wrsd{0}_d3_in<-mkDWire(0);
       GenericIOType  sd{0}_clk_io = GenericIOType{{
                  outputval:wrsd{0}_clk,
                  output_en:1,
@@ -117,7 +130,6 @@ sdwires = '''
                  drivestrength:0,
                  opendrain_en:0
       }};
-      Wire#(Bit#(1)) wrsd{0}_cmd<-mkDWire(0);
       GenericIOType  sd{0}_cmd_io = GenericIOType{{
                  outputval:wrsd{0}_cmd,
                  output_en:1,
@@ -128,9 +140,6 @@ sdwires = '''
                  drivestrength:0,
                  opendrain_en:0
       }};
-      Wire#(Bit#(1)) wrsd{0}_d0_out<-mkDWire(0);
-      Wire#(Bit#(1)) wrsd{0}_d0_outen<-mkDWire(0);
-      Wire#(Bit#(1)) wrsd{0}_d0_in<-mkDWire(0);
       GenericIOType  sd{0}_d0_io = GenericIOType{{
                  outputval:wrsd{0}_d0_out,
                  output_en:wrsd{0}_d0_outen,
@@ -141,9 +150,6 @@ sdwires = '''
                  drivestrength:0,
                  opendrain_en:0
       }};
-      Wire#(Bit#(1)) wrsd{0}_d1_out<-mkDWire(0);
-      Wire#(Bit#(1)) wrsd{0}_d1_outen<-mkDWire(0);
-      Wire#(Bit#(1)) wrsd{0}_d1_in<-mkDWire(0);
       GenericIOType  sd{0}_d1_io = GenericIOType{{
                  outputval:wrsd{0}_d1_out,
                  output_en:wrsd{0}_d1_outen,
@@ -154,9 +160,6 @@ sdwires = '''
                  drivestrength:0,
                  opendrain_en:0
       }};
-      Wire#(Bit#(1)) wrsd{0}_d2_out<-mkDWire(0);
-      Wire#(Bit#(1)) wrsd{0}_d2_outen<-mkDWire(0);
-      Wire#(Bit#(1)) wrsd{0}_d2_in<-mkDWire(0);
       GenericIOType  sd{0}_d2_io = GenericIOType{{
                  outputval:wrsd{0}_d2_out,
                  output_en:wrsd{0}_d2_outen,
@@ -167,9 +170,6 @@ sdwires = '''
                  drivestrength:0,
                  opendrain_en:0
       }};
-      Wire#(Bit#(1)) wrsd{0}_d3_out<-mkDWire(0);
-      Wire#(Bit#(1)) wrsd{0}_d3_outen<-mkDWire(0);
-      Wire#(Bit#(1)) wrsd{0}_d3_in<-mkDWire(0);
       GenericIOType  sd{0}_d3_io = GenericIOType{{
                  outputval:wrsd{0}_d3_out,
                  output_en:wrsd{0}_d3_outen,
@@ -184,6 +184,10 @@ sdwires = '''
 
 jtagwires = '''
       Wire#(Bit#(1)) wrjtag{0}_tdi<-mkDWire(0);
+      Wire#(Bit#(1)) wrjtag{0}_tms<-mkDWire(0);
+      Wire#(Bit#(1)) wrjtag{0}_tclk<-mkDWire(0);
+      Wire#(Bit#(1)) wrjtag{0}_trst<-mkDWire(0);
+      Wire#(Bit#(1)) wrjtag{0}_tdo<-mkDWire(0);
       GenericIOType jtag{0}_tdi_io=GenericIOType{{
                  outputval:0,
                  output_en:0,
@@ -194,19 +198,17 @@ jtagwires = '''
                  drivestrength:0,
                  opendrain_en:0
       }};
-      Wire#(Bit#(1)) wrjtag{0}_tms<-mkDWire(0);
-      GenericIOType jtag{0}_tms_io=GenericIOType{{
-                 outputval:0,
-                 output_en:0,
-                 input_en:1,
+      GenericIOType jtag{0}_tdo_io=GenericIOType{{
+                 outputval:wrjtag{0}_tdo,
+                 output_en:1,
+                 input_en:0,
                  pullup_en:0,
                  pulldown_en:0,
                  pushpull_en:0,
                  drivestrength:0,
                  opendrain_en:0
       }};
-      Wire#(Bit#(1)) wrjtag{0}_tclk<-mkDWire(0);
-      GenericIOType jtag{0}_tclk_io=GenericIOType{{
+      GenericIOType jtag{0}_tms_io=GenericIOType{{
                  outputval:0,
                  output_en:0,
                  input_en:1,
@@ -216,7 +218,6 @@ jtagwires = '''
                  drivestrength:0,
                  opendrain_en:0
       }};
-      Wire#(Bit#(1)) wrjtag{0}_trst<-mkDWire(0);
       GenericIOType jtag{0}_trst_io=GenericIOType{{
                  outputval:0,
                  output_en:0,
@@ -227,11 +228,10 @@ jtagwires = '''
                  drivestrength:0,
                  opendrain_en:0
       }};
-      Wire#(Bit#(1)) wrjtag{0}_tdo<-mkDWire(0);
-      GenericIOType jtag{0}_tdo_io=GenericIOType{{
-                 outputval:wrjtag{0}_tdo,
-                 output_en:1,
-                 input_en:0,
+      GenericIOType jtag{0}_tclk_io=GenericIOType{{
+                 outputval:0,
+                 output_en:0,
+                 input_en:1,
                  pullup_en:0,
                  pulldown_en:0,
                  pushpull_en:0,