From: lkcl <lkcl@web>
Date: Wed, 5 Oct 2022 22:59:24 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~147
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b129db56f5b162ed36455bcbd56d6510c2178483;p=libreriscv.git

---

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index e3b44a386..73280b1d5 100644
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -81,7 +81,7 @@ SVP64 RM `MODE` (includes `ELWIDTH_SRC` bits) for CR-based operations:
 | / | / | 0 RG  |   0 | dz  sz  | simple mode                      |
 | / | / | 0 RG  |   1 | dz  sz  | scalar reduce mode (mapreduce) |
 |zz |SNZ| 1 VLI | inv |  CR-bit | Ffirst 3-bit mode      |
-| / |SNZ| 1 VLI | inv |  dz sz  | Ffirst 5-bit mode (implies CR-bit=EQ) |
+| / |SNZ| 1 VLI | inv |  dz sz  | Ffirst 5-bit mode (implies CR-bit from result) |
 
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