From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 3 Nov 2020 13:53:28 +0000 (+0000)
Subject: swap wires around to match ulx3s
X-Git-Tag: convert-csv-opcode-to-binary~1882
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b12db26ac0451096c00abfebd0444e10ddcfae4e;p=libreriscv.git

swap wires around to match ulx3s
---

diff --git a/HDL_workflow/ECP5_FPGA.mdwn b/HDL_workflow/ECP5_FPGA.mdwn
index e4d7f8235..0dcff636e 100644
--- a/HDL_workflow/ECP5_FPGA.mdwn
+++ b/HDL_workflow/ECP5_FPGA.mdwn
@@ -172,10 +172,10 @@ Table of connections:
 |1 GND        | GND         | GND            |   Black   |
 |2 NC         |NOT CONNECTED| NOT CONNECTED  |    NC     |
 |3 +2V5       | 2.5V supply | 2 (MCU VDD)    |   Red     |
-|4 IO29       |  B19        |    9 (TCK)     |   Black   |
-|5 IO30       |  B12        |    7 (TMS)     |   Green   |
-|6 IO31       |  B9         |    5 (TDI)     |   Blue    |
-|7 IO32       |  E6         |   13 (TDO)     |   White   |
+|4 IO29       |  B19        |    5 (TDI)     |   Green   |
+|5 IO30       |  B12        |    7 (TMS)     |   Blue    |
+|6 IO31       |  B9         |    9 (TCK)     |   White   |
+|7 IO32       |  E6         |   13 (TDO)     |   Yellow  |
 
 [[!img 2020-11-03_13-22.png size="900x" ]]