From: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Date: Tue, 25 Jun 2019 11:25:32 +0000 (+0200)
Subject: radv/gfx10: implement radv_pipeline_generate_geometry_shader()
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b144a70ca832909d6c6ffb52c8f4ee6880f0e1f7;p=mesa.git

radv/gfx10: implement radv_pipeline_generate_geometry_shader()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
---

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 79d71d2259e..44de1aad674 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3210,9 +3210,15 @@ radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
 	va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
 
 	if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
-		radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
-		radeon_emit(cs, va >> 8);
-		radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
+		if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
+			radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
+			radeon_emit(cs, va >> 8);
+			radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
+		} else {
+			radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
+			radeon_emit(cs, va >> 8);
+			radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
+		}
 
 		radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
 		radeon_emit(cs, gs->config.rsrc1);