From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Fri, 8 Jun 2012 15:52:32 +0000 (+0200)
Subject: sim: multiread/multiwrite
X-Git-Tag: 24jan2021_ls180~2099^2~937
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b145f9e5e2b0e1936fb19d3b483c718b64594696;p=litex.git

sim: multiread/multiwrite
---

diff --git a/migen/sim/generic.py b/migen/sim/generic.py
index 323f62ff..d503289a 100644
--- a/migen/sim/generic.py
+++ b/migen/sim/generic.py
@@ -139,7 +139,28 @@ class Simulator:
 			value += 2**nbits
 		assert(value >= 0 and value < 2**nbits)
 		self.ipc.send(MessageWrite(name, Int32(index), value))
+	
+	def multiread(self, obj):
+		if isinstance(obj, Signal):
+			return self.rd(obj)
+		elif isinstance(obj, list):
+			return [self.multiread(item) for item in obj]
+		elif hasattr(obj, "__dict__"):
+			return dict([(k, self.multiread(v)) for k, v in obj.__dict__.items()])
+	
+	def multiwrite(self, obj, value):
+		if isinstance(obj, Signal):
+			self.wr(obj, value)
+		elif isinstance(obj, list):
+			for target, source in zip(obj, value):
+				self.multiwrite(target, source)
+		else:
+			for k, v in value.items():
+				self.multiwrite(getattr(obj, k), v)
+
 
+# Contrary to multiread/multiwrite, Proxy fetches the necessary signals only and
+# immediately forwards writes into the simulation.
 class Proxy:
 	def __init__(self, sim, obj):
 		self.__dict__["_sim"] = sim