From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 17 May 2022 02:37:54 +0000 (-0700)
Subject: scale images down
X-Git-Tag: opf_rfc_ls005_v1~2185
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b148f1c023f3a22929e32700a7f5c5f600fe01a2;p=libreriscv.git

scale images down
---

diff --git a/openpower/sv/bitmanip/grev_gorc_design.mdwn b/openpower/sv/bitmanip/grev_gorc_design.mdwn
index 879e7d268..dbb71d4a4 100644
--- a/openpower/sv/bitmanip/grev_gorc_design.mdwn
+++ b/openpower/sv/bitmanip/grev_gorc_design.mdwn
@@ -2,17 +2,17 @@
 
 The design is derived from a circuit for GRev made with muxes:
 
-![grev_made_with_muxes.svg](../grev_made_with_muxes.svg)
+<img src="../grev_made_with_muxes.svg" width="50%" height="50%"/>
 
 First, we convert that circuit to use And-Or-Invert gates, since that's an efficient way the muxes can be implemented:
 
-![grev_made_with_aoi_gates.svg](../grev_made_with_aoi_gates.svg)
+<img src="../grev_made_with_aoi_gates.svg" width="50%" height="50%" />
 
 Notice how each And-Or-Invert has both a bit of `SH` and `~SH` as inputs? Those can be converted to separate inputs, controlled by the bits of `SH` using the instruction's immediate as a pair of 2-bit look-up-tables. This requires 4-bits of immediate.
 
 This gives us our final design:
 
-![grev_gorc_combination.svg](../grev_gorc_combination.svg)
+<img src="../grev_gorc_combination.svg" width="50%" height="50%" />
 
 Notice how this still has an overall circuit latency that is essentially equivalent to grev's latency (or shift/rotate's latency). Also notice how this circuit allows specifying much more than just `grev` or `gorc` instructions. A final layer of XOR gates can be added at the input and output, allowing it to function as a `gandc` instruction too, requiring a total of 6-bits of immediate.