From: Kevin Lim <ktlim@umich.edu>
Date: Mon, 24 Apr 2006 20:59:50 +0000 (-0400)
Subject: Fixes for ll/sc for the O3 model.
X-Git-Tag: m5_2.0_beta1~36^2~108^2~42
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b14bf0321947419603610f07ed4f14b51a2192a3;p=gem5.git

Fixes for ll/sc for the O3 model.

cpu/o3/alpha_cpu.hh:
    Store conditionals should not write their data to memory if they failed.
cpu/o3/lsq_unit.hh:
    Setup request parameters when they're needed.

--HG--
extra : convert_revision : d75cd7deda03584b7e25cb567e4d79032cac7118
---

diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh
index 68e149e77..dfdf092ed 100644
--- a/cpu/o3/alpha_cpu.hh
+++ b/cpu/o3/alpha_cpu.hh
@@ -425,9 +425,10 @@ class AlphaFullCPU : public FullO3CPU<Impl>
                 req->result = 2;
             } else {
                 if (this->lockFlag/* && this->lockAddr == req->paddr*/) {
-                    req->result=1;
+                    req->result = 1;
                 } else {
                     req->result = 0;
+                    return NoFault;
                 }
             }
         }
diff --git a/cpu/o3/lsq_unit.hh b/cpu/o3/lsq_unit.hh
index 73c485ce9..ba8b1d2e2 100644
--- a/cpu/o3/lsq_unit.hh
+++ b/cpu/o3/lsq_unit.hh
@@ -566,6 +566,9 @@ LSQUnit<Impl>::read(MemReqPtr &req, T &data, int load_idx)
     DPRINTF(LSQUnit, "Doing functional access for inst PC %#x\n",
             loadQueue[load_idx]->readPC());
     assert(!req->data);
+    req->cmd = Read;
+    req->completionEvent = NULL;
+    req->time = curTick;
     req->data = new uint8_t[64];
     Fault fault = cpu->read(req, data);
     memcpy(req->data, &data, sizeof(T));
@@ -587,9 +590,6 @@ LSQUnit<Impl>::read(MemReqPtr &req, T &data, int load_idx)
         }
         DPRINTF(LSQUnit, "Doing timing access for inst PC %#x\n",
                 loadQueue[load_idx]->readPC());
-        req->cmd = Read;
-        req->completionEvent = NULL;
-        req->time = curTick;
 
         assert(!req->completionEvent);
         req->completionEvent =