From: whitequark <cz@m-labs.hk>
Date: Mon, 31 Dec 2018 03:37:38 +0000 (+0000)
Subject: back.rtlil: fix typo.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b14e5a0ff21276be3c70b5cb9b9973e4d5df3caf;p=nmigen.git

back.rtlil: fix typo.
---

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index 9ad3033..10ff80f 100644
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -557,7 +557,7 @@ class _StatementCompiler(xfrm.StatementVisitor):
         else:
             # In RTLIL, LHS and RHS of assignment must have exactly same width.
             rhs_sigspec = self.rhs_compiler.match_shape(
-                stmt.rhs, lhs_bits, rhs_sign)
+                stmt.rhs, lhs_bits, lhs_sign)
         self._case.assign(self.lhs_compiler(stmt.lhs), rhs_sigspec)
 
     def on_Switch(self, stmt):