From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 22 Jul 2022 14:08:57 +0000 (+0100)
Subject: add AVX512 and RVV
X-Git-Tag: opf_rfc_ls005_v1~1140
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b1565370c978fe821de58966dc8025a483850967;p=libreriscv.git

add AVX512 and RVV
---

diff --git a/openpower/sv/comparison_table.mdwn b/openpower/sv/comparison_table.mdwn
index a79c8c07c..f4eff592d 100644
--- a/openpower/sv/comparison_table.mdwn
+++ b/openpower/sv/comparison_table.mdwn
@@ -1,11 +1,13 @@
 # ISA Comparison Table
 
-| Name | Num <br />opcodes | Class         | Predicate <br /> Masks | Twin <br /> Predication |  Explicit <br /> Vector regs | 128-bit | Bigint <br /> capability | LDST <br /> Fault-First | Data-dependent <br /> Fail-first | Predicate-<br /> Result |
-|------|-------------------|---------------|------------------------|-------------------------|------------------------------|---------|--------------------------|-------------------------|----------------------------------|-------------------------|
-| SVP64| 5{1}              | Scalable{2}   | yes                    | yes{3}                  | no{4}                        | n/a{5}  | yes{6}                   | yes{7}                  | yes{8}                           | yes{9}                  |
-| VSX  | 700+              | PackedSIMD    | no                     | no                      | yes{10}                      | yes     | no                       | no                      | no                               | no                      |
-| NEON | ~250{11}          | PredicatedSIMD| yes                    | no                      | yes                          | yes     | no                       | no                      | no                               | no                      |
-| SVE2 | ~1000{12}         | HSCalable{13} | yes                    | no                      | yes                          | yes     | no                       | no                      | no                               | no                      |
+| Name        | Num <br />opcodes | Class         | Predicate <br /> Masks | Twin <br /> Predication |  Explicit <br /> Vector regs | 128-bit | Bigint <br /> capability | LDST <br /> Fault-First | Data-dependent <br /> Fail-first | Predicate-<br /> Result |
+|-------------|-------------------|---------------|------------------------|-------------------------|------------------------------|---------|--------------------------|-------------------------|----------------------------------|-------------------------|
+| SVP64       | 5{1}              | Scalable{2}   | yes                    | yes{3}                  | no{4}                        | n/a{5}  | yes{6}                   | yes{7}                  | yes{8}                           | yes{9}                  |
+| VSX         | 700+              | PackedSIMD    | no                     | no                      | yes{10}                      | yes     | no                       | no                      | no                               | no                      |
+| NEON        | ~250{11}          | PredicatedSIMD| yes                    | no                      | yes                          | yes     | no                       | no                      | no                               | no                      |
+| SVE2        | ~1000{12}         | HSCalable{13} | yes                    | no                      | yes                          | yes     | no                       | yes{7}                  | no                               | no                      |
+| AVX-512{14} | ~1000s{15}        | PredicatedSIMD| yes                    | no                      | yes                          | yes     | no                       | no                      | no                               | no                      |
+| RVV{16}     | ~190              | Scalable{17}  | yes                    | no                      | yes                          | yes{18} | no                       | yes                     | no                               | no                      |
 
 * {1}: plus EXT001 24-bit prefixing. See [[sv/svp64]]
 * {2}: A 2-Dimensional Scalable Vector ISA with both Horizontal-First and Vertical-First Modes. See [[sv/vector_isa_comparison]]
@@ -22,3 +24,8 @@
 * {12} difficult to exactly ascertain, see ARM Architecture Reference Manual Supplement, DDI 0584.  Critically depends on ARM Scalar instructions.
 * {13}: ARM states that the Scalability is a [Silicon-partner choice](https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/102340_0001_00_en_introduction-to-sve2.pdf?revision=aae96dd2-5334-4ad3-9a47-393086a20fea).
   this "Scalability independence" is not entirely extended in full to the programmer although ARM requests developers to consider it so, in practice this does not happen.
+* {14}: [Wikipedia](https://en.wikipedia.org/wiki/AVX-512), [Lifecycle of an instruction set](https://media.handmade-seattle.com/tom-forsyth/) including full slides
+* {15}: difficult to exactly ascertain, contains subsets. Critically depends on ISA support from earlier x86 ISA subsets (several more thousand instructions). See [SIMD ISA listing](https://www.officedaytime.com/simd512e/)
+* {16}: [RVV Spec](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc)
+* {17}: Like the original Cray RVV is a truly scalable Vector ISA (Cray setvl instruction).
+* {18}: like SVP64 it is up to the hardware implementor to choose whether to support 128-bit elements.