From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 9 Mar 2015 22:29:06 +0000 (+0100)
Subject: uart/sim: add pty (optional, to use flterm)
X-Git-Tag: 24jan2021_ls180~2496
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b157031e8a17710dd06f09418d3a5190abf1267d;p=litex.git

uart/sim: add pty (optional, to use flterm)
---

diff --git a/misoclib/com/uart/phy/sim.py b/misoclib/com/uart/phy/sim.py
index c628ea92..faae3d6e 100644
--- a/misoclib/com/uart/phy/sim.py
+++ b/misoclib/com/uart/phy/sim.py
@@ -1,3 +1,5 @@
+import os, pty, time
+
 from migen.fhdl.std import *
 from migen.flow.actor import Sink, Source
 
@@ -15,3 +17,14 @@ class UARTPHYSim(Module):
 			self.source.data.eq(pads.sink_data),
 			pads.sink_ack.eq(self.source.ack)
 		]
+
+		m, s = pty.openpty()
+		name = os.ttyname(s)
+		print("UART tty: "+name)
+		time.sleep(0.5) # pause for user
+		f = open("/tmp/simserial", "w")
+		f.write(os.ttyname(s))
+		f.close()
+
+	def do_exit(self, *args, **kwargs):
+		os.remove("/tmp/simserial")