From: Kenneth Graunke Date: Wed, 3 Aug 2016 03:58:30 +0000 (-0700) Subject: i965: Bail on the BLT path if BlitFramebuffer requires sRGB conversion. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b1586526e84ab6eab2023b589da8e153f70dda50;p=mesa.git i965: Bail on the BLT path if BlitFramebuffer requires sRGB conversion. Modern OpenGL BlitFramebuffer require sRGB encode/decode when GL_FRAMEBUFFER_SRGB is enabled. The blitter can't handle this, so we need to bail. On Gen4-5, this means falling back to Meta, which should handle it. We allow sRGB <-> sRGB blits, as decode then encode ought to be a noop (other than potential precision loss, which nobody wants anyway). Signed-off-by: Kenneth Graunke Reviewed-by: Ian Romanick --- diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c index 23e1ab62c4f..8df5b4871cc 100644 --- a/src/mesa/drivers/dri/i965/intel_blit.c +++ b/src/mesa/drivers/dri/i965/intel_blit.c @@ -211,8 +211,8 @@ intel_miptree_blit(struct brw_context *brw, return false; /* No sRGB decode or encode is done by the hardware blitter, which is - * consistent with what we want in the callers (glCopyTexSubImage(), - * glBlitFramebuffer(), texture validation, etc.). + * consistent with what we want in many callers (glCopyTexSubImage(), + * texture validation, etc.). */ mesa_format src_format = _mesa_get_srgb_format_linear(src_mt->format); mesa_format dst_format = _mesa_get_srgb_format_linear(dst_mt->format); diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c index 707a9d2af3d..573c3a854cd 100644 --- a/src/mesa/drivers/dri/i965/intel_fbo.c +++ b/src/mesa/drivers/dri/i965/intel_fbo.c @@ -828,6 +828,14 @@ intel_blit_framebuffer_with_blitter(struct gl_context *ctx, return mask; } + if (ctx->Color.sRGBEnabled && + _mesa_get_format_color_encoding(src_irb->mt->format) != + _mesa_get_format_color_encoding(dst_irb->mt->format)) { + perf_debug("glBlitFramebuffer() with sRGB conversion cannot be " + "handled by BLT path.\n"); + return mask; + } + if (!intel_miptree_blit(brw, src_irb->mt, src_irb->mt_level, src_irb->mt_layer,