From: Gabe Black <gblack@eecs.umich.edu>
Date: Thu, 16 Feb 2006 06:25:48 +0000 (-0500)
Subject: Merge gblack@m5.eecs.umich.edu:/bk/multiarch
X-Git-Tag: m5_2.0_beta1~87^2~97^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b161d2a731ec7d75bdeb896d1b89efcbb125a09f;p=gem5.git

Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into  ewok.(none):/home/gblack/m5/multiarch

--HG--
extra : convert_revision : d8626acb2686e123ad0bb6cf94e85c992657470d
---

b161d2a731ec7d75bdeb896d1b89efcbb125a09f
diff --cc arch/alpha/isa/mem.isa
index 1889daefc,1f6907181..19785e3a8
--- a/arch/alpha/isa/mem.isa
+++ b/arch/alpha/isa/mem.isa
@@@ -282,56 -267,8 +282,56 @@@ def template LoadExecute {
  }};
  
  
 +def template LoadInitiateAcc {{
 +    Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
 +                                      Trace::InstRecord *traceData) const
 +    {
 +        Addr EA;
 +        Fault fault = No_Fault;
 +        %(mem_acc_type)s Mem = 0;
 +
 +        %(fp_enable_check)s;
 +        %(op_src_decl)s;
 +        %(op_rd)s;
 +        %(ea_code)s;
 +
 +        if (fault == No_Fault) {
 +            fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
 +        }
 +
 +        return fault;
 +    }
 +}};
 +
 +
 +def template LoadCompleteAcc {{
 +    Fault %(class_name)s::completeAcc(uint8_t *data,
 +                                      %(CPU_exec_context)s *xc,
 +                                      Trace::InstRecord *traceData) const
 +    {
 +        Fault fault = No_Fault;
 +        %(mem_acc_type)s Mem = 0;
 +
 +        %(fp_enable_check)s;
 +        %(op_dest_decl)s;
 +
 +        memcpy(&Mem, data, sizeof(Mem));
 +
 +        if (fault == No_Fault) {
 +            %(memacc_code)s;
 +        }
 +
 +        if (fault == No_Fault) {
 +            %(op_wb)s;
 +        }
 +
 +        return fault;
 +    }
 +}};
 +
 +
  def template StoreMemAccExecute {{
-     Fault
+     Fault *
      %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
                                     Trace::InstRecord *traceData) const
      {
@@@ -402,63 -339,9 +402,63 @@@ def template StoreExecute {
      }
  }};
  
 +def template StoreInitiateAcc {{
 +    Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
 +                                      Trace::InstRecord *traceData) const
 +    {
 +        Addr EA;
 +        Fault fault = No_Fault;
 +        uint64_t write_result = 0;
 +        %(mem_acc_type)s Mem = 0;
 +
 +        %(fp_enable_check)s;
 +        %(op_src_decl)s;
 +        %(op_rd)s;
 +        %(ea_code)s;
 +
 +        if (fault == No_Fault) {
 +            %(memacc_code)s;
 +        }
 +
 +        if (fault == No_Fault) {
 +            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
 +                              memAccessFlags, &write_result);
 +            if (traceData) { traceData->setData(Mem); }
 +        }
 +
 +        return fault;
 +    }
 +}};
 +
 +
 +def template StoreCompleteAcc {{
 +    Fault %(class_name)s::completeAcc(uint8_t *data,
 +                                      %(CPU_exec_context)s *xc,
 +                                      Trace::InstRecord *traceData) const
 +    {
 +        Fault fault = No_Fault;
 +        uint64_t write_result = 0;
 +
 +        %(fp_enable_check)s;
 +        %(op_dest_decl)s;
 +
 +        memcpy(&write_result, data, sizeof(write_result));
 +
 +        if (fault == No_Fault) {
 +            %(postacc_code)s;
 +        }
 +
 +        if (fault == No_Fault) {
 +            %(op_wb)s;
 +        }
 +
 +        return fault;
 +    }
 +}};
 +
  
  def template MiscMemAccExecute {{
-     Fault %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
+     Fault * %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
                                            Trace::InstRecord *traceData) const
      {
          Addr EA;