From: Gabe Black Date: Sat, 17 Aug 2019 08:32:23 +0000 (-0700) Subject: cpu: Move the instruction port into o3's fetch stage. X-Git-Tag: v19.0.0.0~624 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b16e525e4073b27f70bf6cf960313ea76cf6ed54;p=gem5.git cpu: Move the instruction port into o3's fetch stage. That's where it's used, and that avoids having to pass it around using the top level getInstPort accessor. Change-Id: I489a3f3239b3116292f3dcd78a3945fb468c6311 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20239 Tested-by: kokoro Reviewed-by: Jason Lowe-Power Reviewed-by: Andreas Sandberg Maintainer: Gabe Black --- diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index c9e01a5c2..1353c1ed4 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -90,26 +90,6 @@ BaseO3CPU::regStats() BaseCPU::regStats(); } -template -bool -FullO3CPU::IcachePort::recvTimingResp(PacketPtr pkt) -{ - DPRINTF(O3CPU, "Fetch unit received timing\n"); - // We shouldn't ever get a cacheable block in Modified state - assert(pkt->req->isUncacheable() || - !(pkt->cacheResponding() && !pkt->hasSharers())); - fetch->processCacheCompletion(pkt); - - return true; -} - -template -void -FullO3CPU::IcachePort::recvReqRetry() -{ - fetch->recvReqRetry(); -} - template FullO3CPU::FullO3CPU(DerivO3CPUParams *params) : BaseO3CPU(params), @@ -148,8 +128,6 @@ FullO3CPU::FullO3CPU(DerivO3CPUParams *params) isa(numThreads, NULL), - icachePort(&fetch, this), - timeBuffer(params->backComSize, params->forwardComSize), fetchQueue(params->backComSize, params->forwardComSize), decodeQueue(params->backComSize, params->forwardComSize), @@ -172,7 +150,7 @@ FullO3CPU::FullO3CPU(DerivO3CPUParams *params) if (params->checker) { BaseCPU *temp_checker = params->checker; checker = dynamic_cast *>(temp_checker); - checker->setIcachePort(&icachePort); + checker->setIcachePort(&this->fetch.getInstPort()); checker->setSystem(params->system); } else { checker = NULL; diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 778c55bac..58a22184d 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -133,31 +133,6 @@ class FullO3CPU : public BaseO3CPU private: - /** - * IcachePort class for instruction fetch. - */ - class IcachePort : public MasterPort - { - protected: - /** Pointer to fetch. */ - DefaultFetch *fetch; - - public: - /** Default constructor. */ - IcachePort(DefaultFetch *_fetch, FullO3CPU* _cpu) - : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch) - { } - - protected: - - /** Timing version of receive. Handles setting fetch to the - * proper status to start fetching. */ - virtual bool recvTimingResp(PacketPtr pkt); - - /** Handles doing a retry of a failed fetch. */ - virtual void recvReqRetry(); - }; - /** The tick event used for scheduling CPU ticks. */ EventFunctionWrapper tickEvent; @@ -629,9 +604,6 @@ class FullO3CPU : public BaseO3CPU std::vector isa; - /** Instruction port. Note that it has to appear after the fetch stage. */ - IcachePort icachePort; - public: /** Enum to give each stage a specific index, so when calling * activateStage() or deactivateStage(), they can specify which stage @@ -763,7 +735,11 @@ class FullO3CPU : public BaseO3CPU } /** Used by the fetch unit to get a hold of the instruction port. */ - MasterPort &getInstPort() override { return icachePort; } + MasterPort & + getInstPort() override + { + return this->fetch.getInstPort(); + } /** Get the dcache port (used to find block size for translations). */ MasterPort & diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh index 3cf0773fd..b8766ad77 100644 --- a/src/cpu/o3/fetch.hh +++ b/src/cpu/o3/fetch.hh @@ -59,6 +59,8 @@ #include "sim/probe/probe.hh" struct DerivO3CPUParams; +template +class FullO3CPU; /** * DefaultFetch class handles both single threaded and SMT fetch. Its @@ -85,6 +87,31 @@ class DefaultFetch /** Typedefs from ISA. */ typedef TheISA::MachInst MachInst; + /** + * IcachePort class for instruction fetch. + */ + class IcachePort : public MasterPort + { + protected: + /** Pointer to fetch. */ + DefaultFetch *fetch; + + public: + /** Default constructor. */ + IcachePort(DefaultFetch *_fetch, FullO3CPU* _cpu) + : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch) + { } + + protected: + + /** Timing version of receive. Handles setting fetch to the + * proper status to start fetching. */ + virtual bool recvTimingResp(PacketPtr pkt); + + /** Handles doing a retry of a failed fetch. */ + virtual void recvReqRetry(); + }; + class FetchTranslation : public BaseTLB::Translation { protected: @@ -353,6 +380,8 @@ class DefaultFetch /** The decoder. */ TheISA::Decoder *decoder[Impl::MaxThreads]; + MasterPort &getInstPort() { return icachePort; } + private: DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst, StaticInstPtr curMacroop, TheISA::PCState thisPC, @@ -511,6 +540,9 @@ class DefaultFetch */ bool interruptPending; + /** Instruction port. Note that it has to appear after the fetch stage. */ + IcachePort icachePort; + /** Set to true if a pipelined I-cache request should be issued. */ bool issuePipelinedIfetch[Impl::MaxThreads]; diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index f0a97e429..60542b824 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -60,11 +60,13 @@ #include "config/the_isa.hh" #include "cpu/base.hh" //#include "cpu/checker/cpu.hh" +#include "cpu/o3/cpu.hh" #include "cpu/o3/fetch.hh" #include "cpu/exetrace.hh" #include "debug/Activity.hh" #include "debug/Drain.hh" #include "debug/Fetch.hh" +#include "debug/O3CPU.hh" #include "debug/O3PipeView.hh" #include "mem/packet.hh" #include "params/DerivO3CPU.hh" @@ -96,6 +98,7 @@ DefaultFetch::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params) fetchQueueSize(params->fetchQueueSize), numThreads(params->numThreads), numFetchingThreads(params->smtNumFetchingThreads), + icachePort(this, _cpu), finishTranslationEvent(this) { if (numThreads > Impl::MaxThreads) @@ -692,7 +695,7 @@ DefaultFetch::finishTranslation(const Fault &fault, fetchedCacheLines++; // Access the cache. - if (!cpu->getInstPort().sendTimingReq(data_pkt)) { + if (!icachePort.sendTimingReq(data_pkt)) { assert(retryPkt == NULL); assert(retryTid == InvalidThreadID); DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid); @@ -1422,7 +1425,7 @@ DefaultFetch::recvReqRetry() assert(retryTid != InvalidThreadID); assert(fetchStatus[retryTid] == IcacheWaitRetry); - if (cpu->getInstPort().sendTimingReq(retryPkt)) { + if (icachePort.sendTimingReq(retryPkt)) { fetchStatus[retryTid] = IcacheWaitResponse; // Notify Fetch Request probe when a retryPkt is successfully sent. // Note that notify must be called before retryPkt is set to NULL. @@ -1670,4 +1673,24 @@ DefaultFetch::profileStall(ThreadID tid) { } } +template +bool +DefaultFetch::IcachePort::recvTimingResp(PacketPtr pkt) +{ + DPRINTF(O3CPU, "Fetch unit received timing\n"); + // We shouldn't ever get a cacheable block in Modified state + assert(pkt->req->isUncacheable() || + !(pkt->cacheResponding() && !pkt->hasSharers())); + fetch->processCacheCompletion(pkt); + + return true; +} + +template +void +DefaultFetch::IcachePort::recvReqRetry() +{ + fetch->recvReqRetry(); +} + #endif//__CPU_O3_FETCH_IMPL_HH__