From: Nathan Binkert Date: Sun, 12 Nov 2006 01:22:10 +0000 (-0800) Subject: Get rid of the ParamContext for pseudo instructions and move X-Git-Tag: m5_2.0_beta2~61 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b16e5591773c362f10808ab439b27a87d891f0fc;p=gem5.git Get rid of the ParamContext for pseudo instructions and move the parameters to the BaseCPU object. --HG-- extra : convert_revision : 557292cffb40918133647b0c9ac653ee5112df2e --- diff --git a/src/cpu/base.hh b/src/cpu/base.hh index 9257778ef..788f77e3a 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -155,6 +155,10 @@ class BaseCPU : public MemObject int cpu_id; #if FULL_SYSTEM Tick profile; + + bool do_statistics_insts; + bool do_checkpoint_insts; + bool do_quiesce; #endif Tick progress_interval; BaseCPU *checker; diff --git a/src/cpu/o3/alpha/cpu_builder.cc b/src/cpu/o3/alpha/cpu_builder.cc index be8ad8de6..09ccc7f65 100644 --- a/src/cpu/o3/alpha/cpu_builder.cc +++ b/src/cpu/o3/alpha/cpu_builder.cc @@ -57,6 +57,10 @@ Param cpu_id; SimObjectParam itb; SimObjectParam dtb; Param profile; + +Param do_quiesce; +Param do_checkpoint_insts; +Param do_statistics_insts; #else SimObjectVectorParam workload; #endif // FULL_SYSTEM @@ -163,6 +167,10 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU) INIT_PARAM(itb, "Instruction translation buffer"), INIT_PARAM(dtb, "Data translation buffer"), INIT_PARAM(profile, ""), + + INIT_PARAM(do_quiesce, ""), + INIT_PARAM(do_checkpoint_insts, ""), + INIT_PARAM(do_statistics_insts, ""), #else INIT_PARAM(workload, "Processes to run"), #endif // FULL_SYSTEM @@ -306,6 +314,10 @@ CREATE_SIM_OBJECT(DerivO3CPU) params->itb = itb; params->dtb = dtb; params->profile = profile; + + params->do_quiesce = do_quiesce; + params->do_checkpoint_insts = do_checkpoint_insts; + params->do_statistics_insts = do_statistics_insts; #else params->workload = workload; #endif // FULL_SYSTEM diff --git a/src/cpu/ozone/cpu_builder.cc b/src/cpu/ozone/cpu_builder.cc index 39337dbff..155f0ce09 100644 --- a/src/cpu/ozone/cpu_builder.cc +++ b/src/cpu/ozone/cpu_builder.cc @@ -64,6 +64,10 @@ Param cpu_id; SimObjectParam itb; SimObjectParam dtb; Param profile; + +Param do_quiesce; +Param do_checkpoint_insts; +Param do_statistics_insts #else SimObjectVectorParam workload; //SimObjectParam page_table; @@ -184,6 +188,9 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU) INIT_PARAM(itb, "Instruction translation buffer"), INIT_PARAM(dtb, "Data translation buffer"), INIT_PARAM(profile, ""), + INIT_PARAM(do_quiesce, ""), + INIT_PARAM(do_checkpoint_insts, ""), + INIT_PARAM(do_statistics_insts, ""), #else INIT_PARAM(workload, "Processes to run"), // INIT_PARAM(page_table, "Page table"), @@ -341,6 +348,9 @@ CREATE_SIM_OBJECT(DerivOzoneCPU) params->itb = itb; params->dtb = dtb; params->profile = profile; + params->do_quiesce = do_quiesce; + params->do_checkpoint_insts = do_checkpoint_insts; + params->do_statistics_insts = do_statistics_insts; #else params->workload = workload; // params->pTable = page_table; diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 4f68cfd6f..e9679cc7c 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -500,6 +500,10 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU) SimObjectParam itb; SimObjectParam dtb; Param profile; + + Param do_quiesce; + Param do_checkpoint_insts; + Param do_statistics_insts; #else SimObjectParam workload; #endif // FULL_SYSTEM @@ -532,6 +536,9 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU) INIT_PARAM(itb, "Instruction TLB"), INIT_PARAM(dtb, "Data TLB"), INIT_PARAM(profile, ""), + INIT_PARAM(do_quiesce, ""), + INIT_PARAM(do_checkpoint_insts, ""), + INIT_PARAM(do_statistics_insts, ""), #else INIT_PARAM(workload, "processes to run"), #endif // FULL_SYSTEM @@ -569,6 +576,9 @@ CREATE_SIM_OBJECT(AtomicSimpleCPU) params->itb = itb; params->dtb = dtb; params->profile = profile; + params->do_quiesce = do_quiesce; + params->do_checkpoint_insts = do_checkpoint_insts; + params->do_statistics_insts = do_statistics_insts; #else params->process = workload; #endif diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index abf316095..db2c940c0 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -665,6 +665,10 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) SimObjectParam itb; SimObjectParam dtb; Param profile; + + Param do_quiesce; + Param do_checkpoint_insts; + Param do_statistics_insts; #else SimObjectParam workload; #endif // FULL_SYSTEM @@ -697,6 +701,9 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) INIT_PARAM(itb, "Instruction TLB"), INIT_PARAM(dtb, "Data TLB"), INIT_PARAM(profile, ""), + INIT_PARAM(do_quiesce, ""), + INIT_PARAM(do_checkpoint_insts, ""), + INIT_PARAM(do_statistics_insts, ""), #else INIT_PARAM(workload, "processes to run"), #endif // FULL_SYSTEM @@ -732,6 +739,9 @@ CREATE_SIM_OBJECT(TimingSimpleCPU) params->itb = itb; params->dtb = dtb; params->profile = profile; + params->do_quiesce = do_quiesce; + params->do_checkpoint_insts = do_checkpoint_insts; + params->do_statistics_insts = do_statistics_insts; #else params->process = workload; #endif diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py index b6e05627d..36474a6a4 100644 --- a/src/python/m5/objects/BaseCPU.py +++ b/src/python/m5/objects/BaseCPU.py @@ -15,6 +15,12 @@ class BaseCPU(SimObject): cpu_id = Param.Int("CPU identifier") if build_env['FULL_SYSTEM']: + do_qiesce = Param.Bool(True, "enable quiesce instructions") + do_checkpoint_insts = Param.Bool(True, + "enable checkpoint pseudo instructions") + do_statistics_insts = Param.Bool(True, + "enable statistics pseudo instructions") + if build_env['TARGET_ISA'] == 'sparc': dtb = Param.SparcDTB(SparcDTB(), "Data TLB") itb = Param.SparcITB(SparcITB(), "Instruction TLB") diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc index 66036def1..4a8c0eb66 100644 --- a/src/sim/pseudo_inst.cc +++ b/src/sim/pseudo_inst.cc @@ -40,7 +40,6 @@ #include "cpu/thread_context.hh" #include "cpu/quiesce_event.hh" #include "arch/kernel_stats.hh" -#include "sim/param.hh" #include "sim/pseudo_inst.hh" #include "sim/serialize.hh" #include "sim/sim_exit.hh" @@ -57,10 +56,6 @@ using namespace TheISA; namespace AlphaPseudo { - bool doStatisticsInsts; - bool doCheckpointInsts; - bool doQuiesce; - void arm(ThreadContext *tc) { @@ -71,7 +66,7 @@ namespace AlphaPseudo void quiesce(ThreadContext *tc) { - if (!doQuiesce) + if (!tc->getCpuPtr()->params->do_quiesce) return; DPRINTF(Quiesce, "%s: quiesce()\n", tc->getCpuPtr()->name()); @@ -84,7 +79,7 @@ namespace AlphaPseudo void quiesceNs(ThreadContext *tc, uint64_t ns) { - if (!doQuiesce || ns == 0) + if (!tc->getCpuPtr()->params->do_quiesce || ns == 0) return; EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent(); @@ -107,7 +102,7 @@ namespace AlphaPseudo void quiesceCycles(ThreadContext *tc, uint64_t cycles) { - if (!doQuiesce || cycles == 0) + if (!tc->getCpuPtr()->params->do_quiesce || cycles == 0) return; EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent(); @@ -197,7 +192,7 @@ namespace AlphaPseudo void resetstats(ThreadContext *tc, Tick delay, Tick period) { - if (!doStatisticsInsts) + if (!tc->getCpuPtr()->params->do_statistics_insts) return; @@ -211,7 +206,7 @@ namespace AlphaPseudo void dumpstats(ThreadContext *tc, Tick delay, Tick period) { - if (!doStatisticsInsts) + if (!tc->getCpuPtr()->params->do_statistics_insts) return; @@ -252,7 +247,7 @@ namespace AlphaPseudo void dumpresetstats(ThreadContext *tc, Tick delay, Tick period) { - if (!doStatisticsInsts) + if (!tc->getCpuPtr()->params->do_statistics_insts) return; @@ -266,7 +261,7 @@ namespace AlphaPseudo void m5checkpoint(ThreadContext *tc, Tick delay, Tick period) { - if (!doCheckpointInsts) + if (!tc->getCpuPtr()->params->do_checkpoint_insts) return; Tick when = curTick + delay * Clock::Int::ns; @@ -278,7 +273,7 @@ namespace AlphaPseudo uint64_t readfile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset) { - const string &file = tc->getCpuPtr()->system->params()->readfile; + const string &file = tc->getSystemPtr()->params()->readfile; if (file.empty()) { return ULL(0); } @@ -310,33 +305,6 @@ namespace AlphaPseudo return result; } - class Context : public ParamContext - { - public: - Context(const string §ion) : ParamContext(section) {} - void checkParams(); - }; - - Context context("pseudo_inst"); - - Param __quiesce(&context, "quiesce", - "enable quiesce instructions", - true); - Param __statistics(&context, "statistics", - "enable statistics pseudo instructions", - true); - Param __checkpoint(&context, "checkpoint", - "enable checkpoint pseudo instructions", - true); - - void - Context::checkParams() - { - doQuiesce = __quiesce; - doStatisticsInsts = __statistics; - doCheckpointInsts = __checkpoint; - } - void debugbreak(ThreadContext *tc) { debug_break();