From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 16 Jul 2014 16:12:46 +0000 (+0200)
Subject: Added "inout" ports support to read_liberty
X-Git-Tag: yosys-0.4~563
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b171a4c1bce1146c890f8238a723a277c8dc2efb;p=yosys.git

Added "inout" ports support to read_liberty
---

diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc
index 398e7a30e..e7af93720 100644
--- a/frontends/liberty/liberty.cc
+++ b/frontends/liberty/liberty.cc
@@ -537,7 +537,7 @@ struct LibertyFrontend : public Frontend {
 			for (auto node : cell->children)
 				if (node->id == "pin" && node->args.size() == 1) {
 					LibertyAst *dir = node->find("direction");
-					if (!dir || (dir->value != "input" && dir->value != "output" && dir->value != "internal"))
+					if (!dir || (dir->value != "input" && dir->value != "output" && dir->value != "inout" && dir->value != "internal"))
 					{
 						if (!flag_ignore_miss_dir)
 						{
@@ -570,6 +570,11 @@ struct LibertyFrontend : public Frontend {
 
 					RTLIL::Wire *wire = module->wires.at(RTLIL::escape_id(node->args.at(0)));
 
+					if (dir && dir->value == "inout") {
+						wire->port_input = true;
+						wire->port_output = true;
+					}
+
 					if (dir && dir->value == "input") {
 						wire->port_input = true;
 						continue;