From: lkcl <lkcl@web>
Date: Mon, 28 Jun 2021 08:59:04 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~705
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b17d4d88aa0a1d9d210557a511a842fc4f1af0f6;p=libreriscv.git

---

diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn
index 4eae60114..1a69d9207 100644
--- a/openpower/sv/vector_ops.mdwn
+++ b/openpower/sv/vector_ops.mdwn
@@ -2,6 +2,8 @@
 
 # SV Vector Operations.
 
+TODO merge old standards page [[simple_v_extension/vector_ops/]]
+
 The core OpenPOWER ISA was designed as scalar: SV provides a level of abstraction to add variable-length element-independent parallelism. However, certain classes of instructions only make sense in a Vector context: AVX512 conflictd for example.  This section includes such examples.  Many of them are from the RISC-V Vector ISA (with thanks to the efforts of RVV's contributors)
 
 Notes: