From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 30 May 2020 00:33:10 +0000 (-0700)
Subject: abc9_ops: optimise to not derive unless attribute exists
X-Git-Tag: working-ls180~507^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b17e8495b83bc8fa13a5ac982b44c0b68d71a68a;p=yosys.git

abc9_ops: optimise to not derive unless attribute exists
---

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 0b799c9f3..22da09e53 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -102,8 +102,6 @@ void check(RTLIL::Design *design, bool dff_mode)
 				auto inst_module = design->module(cell->type);
 				if (!inst_module)
 					continue;
-				if (!inst_module->get_blackbox_attribute())
-					continue;
 				IdString derived_type;
 				Module *derived_module;
 				if (cell->parameters.empty()) {
@@ -111,6 +109,10 @@ void check(RTLIL::Design *design, bool dff_mode)
 					derived_module = inst_module;
 				}
 				else {
+					// Check potential (since its value may depend on a parameter,
+					//   but not its existence)
+					if (!inst_module->has_attribute(ID::abc9_flop))
+						continue;
 					derived_type = inst_module->derive(design, cell->parameters);
 					derived_module = design->module(derived_type);
 					log_assert(derived_module);
@@ -173,8 +175,6 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
 			auto inst_module = design->module(cell->type);
 			if (!inst_module)
 				continue;
-			if (!inst_module->get_blackbox_attribute())
-				continue;
 			IdString derived_type;
 			Module *derived_module;
 			if (cell->parameters.empty()) {
@@ -182,6 +182,10 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
 				derived_module = inst_module;
 			}
 			else {
+				// Check potential for any one of those three
+				//   (since its value may depend on a parameter, but not its existence)
+				if (!inst_module->has_attribute(ID::abc9_flop) && !inst_module->has_attribute(ID::abc9_box) && !inst_module->get_bool_attribute(ID::abc9_bypass))
+					continue;
 				derived_type = inst_module->derive(design, cell->parameters);
 				derived_module = design->module(derived_type);
 			}