From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 12 Nov 2015 18:28:14 +0000 (+0100)
Subject: Changes for Verific 3.16_484_32_151112
X-Git-Tag: yosys-0.6~66
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b18f3a297475203420e6cf204bd4b7ea0f61e44f;p=yosys.git

Changes for Verific 3.16_484_32_151112
---

diff --git a/Makefile b/Makefile
index cc12dc352..aa3703642 100644
--- a/Makefile
+++ b/Makefile
@@ -179,7 +179,7 @@ endif
 
 ifeq ($(ENABLE_VERIFIC),1)
 VERIFIC_DIR ?= /usr/local/src/verific_lib_eval
-VERIFIC_COMPONENTS ?= verilog vhdl database util containers
+VERIFIC_COMPONENTS ?= verilog vhdl database util containers sdf
 CXXFLAGS += $(patsubst %,-I$(VERIFIC_DIR)/%,$(VERIFIC_COMPONENTS)) -DYOSYS_ENABLE_VERIFIC
 LDLIBS += $(patsubst %,$(VERIFIC_DIR)/%/*-linux.a,$(VERIFIC_COMPONENTS))
 endif
diff --git a/frontends/verific/Makefile.inc b/frontends/verific/Makefile.inc
index 13f242c4b..68ef9aed1 100644
--- a/frontends/verific/Makefile.inc
+++ b/frontends/verific/Makefile.inc
@@ -8,8 +8,9 @@ EXTRA_TARGETS += share/verific
 share/verific:
 	$(P) rm -rf share/verific.new
 	$(Q) mkdir -p share/verific.new
-	$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs share/verific.new/vhdl_vdbs_1993
-	$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_2008 share/verific.new/vhdl_vdbs_2008
+	$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_1987/. share/verific.new/vhdl_vdbs_1987
+	$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_1993/. share/verific.new/vhdl_vdbs_1993
+	$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_2008/. share/verific.new/vhdl_vdbs_2008
 	$(Q) mv share/verific.new share/verific
 
 endif
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 9212cc0ff..81640305e 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -841,7 +841,7 @@ struct VerificPass : public Pass {
 		}
 
 		if (args.size() > 1 && args[1] == "-vhdl87") {
-			vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
+			vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1987").c_str());
 			for (size_t argidx = 2; argidx < args.size(); argidx++)
 				if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_87))
 					log_cmd_error("Reading `%s' in VHDL_87 mode failed.\n", args[argidx].c_str());
@@ -918,10 +918,12 @@ struct VerificPass : public Pass {
 
 			for (; argidx < args.size(); argidx++) {
 				if (veri_file::GetModule(args[argidx].c_str())) {
+					log("Running veri_file::Elaborate(\"%s\").\n", args[argidx].c_str());
 					if (!veri_file::Elaborate(args[argidx].c_str()))
 						log_cmd_error("Elaboration of top module `%s' failed.\n", args[argidx].c_str());
 					nl_todo.insert(Netlist::PresentDesign());
 				} else {
+					log("Running vhdl_file::Elaborate(\"%s\").\n", args[argidx].c_str());
 					if (!vhdl_file::Elaborate(args[argidx].c_str()))
 						log_cmd_error("Elaboration of top module `%s' failed.\n", args[argidx].c_str());
 					nl_todo.insert(Netlist::PresentDesign());