From: Gabe Black <gabeblack@google.com>
Date: Tue, 27 Mar 2018 08:24:16 +0000 (-0700)
Subject: cpu: Remove ExtMachInst typedefs from the O3 CPU model.
X-Git-Tag: v19.0.0.0~2197
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b18f7078c3e8e9a32294afe107965f28d498f759;p=gem5.git

cpu: Remove ExtMachInst typedefs from the O3 CPU model.

These typedefs aren't used, and they expose ISA specific types outside
the ISA implementations.

Change-Id: I64b9cec18d6f92765eebbdf8c8f1de15c0deba34
Reviewed-on: https://gem5-review.googlesource.com/9404
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
---

diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 8a0ae1d56..47dc830e0 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -65,8 +65,6 @@ class BaseO3DynInst : public BaseDynInst<Impl>
 
     /** Binary machine instruction type. */
     typedef TheISA::MachInst MachInst;
-    /** Extended machine instruction type. */
-    typedef TheISA::ExtMachInst ExtMachInst;
     /** Register types. */
     typedef TheISA::IntReg   IntReg;
     typedef TheISA::FloatReg FloatReg;
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index 672fb499b..4382197f4 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -83,7 +83,6 @@ class DefaultFetch
 
     /** Typedefs from ISA. */
     typedef TheISA::MachInst MachInst;
-    typedef TheISA::ExtMachInst ExtMachInst;
 
     class FetchTranslation : public BaseTLB::Translation
     {