From: Michael Nolan <mtnolan2640@gmail.com>
Date: Fri, 8 May 2020 20:34:57 +0000 (-0400)
Subject: Add tests for immediates, add subf to tests
X-Git-Tag: div_pipeline~1332
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b198ba3be424e7dfe9dfad5dfb12896f8d764f52;p=soc.git

Add tests for immediates, add subf to tests
---

diff --git a/src/soc/alu/input_stage.py b/src/soc/alu/input_stage.py
index 77da32f5..a692a57a 100644
--- a/src/soc/alu/input_stage.py
+++ b/src/soc/alu/input_stage.py
@@ -6,6 +6,7 @@ from nmigen import (Module, Signal, Cat, Const, Mux, Repl, signed,
                     unsigned)
 from nmutil.pipemodbase import PipeModBase
 from soc.alu.pipe_data import ALUInputData
+from soc.decoder.power_enums import CryIn
 
 
 class ALUInputStage(PipeModBase):
@@ -38,6 +39,14 @@ class ALUInputStage(PipeModBase):
         with m.Else():
             comb += self.o.b.eq(self.i.b)
 
+        with m.Switch(self.i.ctx.op.input_carry):
+            with m.Case(CryIn.ZERO):
+                comb += self.o.carry_in.eq(0)
+            with m.Case(CryIn.ONE):
+                comb += self.o.carry_in.eq(1)
+            with m.Case(CryIn.CA):
+                comb += self.o.carry_in.eq(self.i.carry_in)
+
         comb += self.o.ctx.eq(self.i.ctx)
 
         return m
diff --git a/src/soc/alu/test/test_pipe_caller.py b/src/soc/alu/test/test_pipe_caller.py
index 7c069edb..67da27a6 100644
--- a/src/soc/alu/test/test_pipe_caller.py
+++ b/src/soc/alu/test/test_pipe_caller.py
@@ -43,6 +43,7 @@ def connect_alu(comb, alu, dec2):
     comb += op.data_len.eq(dec2.e.data_len)
     comb += op.byte_reverse.eq(dec2.e.byte_reverse)
     comb += op.sign_extend.eq(dec2.e.sign_extend)
+    comb += op.imm_data.eq(dec2.e.imm_data)
 
 
 
@@ -96,7 +97,7 @@ class ALUTestCase(FHDLTestCase):
                     vld = yield alu.n.valid_o
                 yield
                 alu_out = yield alu.n.data_o.o
-                self.assertEqual(simulator.gpr(3), alu_out)
+                self.assertEqual(simulator.gpr(3), SelectableInt(alu_out, 64))
 
         sim.add_sync_process(process)
         with sim.write_vcd("simulator.vcd", "simulator.gtkw",
@@ -110,8 +111,8 @@ class ALUTestCase(FHDLTestCase):
         return simulator
 
     def test_rand(self):
-        insns = ["add", "add.", "and", "or", "xor"]
-        for i in range(20):
+        insns = ["add", "add.", "and", "or", "xor", "subf"]
+        for i in range(40):
             choice = random.choice(insns)
             lst = [f"{choice} 3, 1, 2"]
             initial_regs = [0] * 32
@@ -120,6 +121,30 @@ class ALUTestCase(FHDLTestCase):
             with Program(lst) as program:
                 sim = self.run_tst_program(program, initial_regs)
 
+    def test_rand_imm(self):
+        insns = ["addi", "addis", "subfic"]
+        for i in range(10):
+            choice = random.choice(insns)
+            imm = random.randint(-(1<<15), (1<<15)-1)
+            lst = [f"{choice} 3, 1, {imm}"]
+            print(lst)
+            initial_regs = [0] * 32
+            initial_regs[1] = random.randint(0, (1<<64)-1)
+            with Program(lst) as program:
+                sim = self.run_tst_program(program, initial_regs)
+
+    def test_rand_imm_logical(self):
+        insns = ["andi.", "andis.", "ori", "oris", "xori", "xoris"]
+        for i in range(10):
+            choice = random.choice(insns)
+            imm = random.randint(0, (1<<16)-1)
+            lst = [f"{choice} 3, 1, {imm}"]
+            print(lst)
+            initial_regs = [0] * 32
+            initial_regs[1] = random.randint(0, (1<<64)-1)
+            with Program(lst) as program:
+                sim = self.run_tst_program(program, initial_regs)
+
     def test_ilang(self):
         rec = CompALUOpSubset()