From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 27 May 2021 10:35:11 +0000 (+0100)
Subject: report log expected different qemu values rather than all of them
X-Git-Tag: xlen-bcd~533
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b19a61f4550e8e2785afb35240043be7ae99958f;p=openpower-isa.git

report log expected different qemu values rather than all of them
---

diff --git a/src/openpower/decoder/isa/pypowersim.py b/src/openpower/decoder/isa/pypowersim.py
index 52074b8b..788867ca 100644
--- a/src/openpower/decoder/isa/pypowersim.py
+++ b/src/openpower/decoder/isa/pypowersim.py
@@ -104,13 +104,15 @@ def qemu_register_compare(sim, qemu, regs, fprs):
     for reg in regs:
         qemu_val = qemu.get_gpr(reg)
         sim_val = sim.gpr(reg).value
-        log("expect %x got %x" % (qemu_val, sim_val))
+        if qemu_val != sim_val:
+            log("expect gpr %d %x got %x" % (gpr, qemu_val, sim_val))
         #self.assertEqual(qemu_val, sim_val,
         #                 "expect %x got %x" % (qemu_val, sim_val))
     for fpr in fprs:
         qemu_val = qemu.get_fpr(fpr)
         sim_val = sim.fpr(fpr).value
-        log("expect fpr %x got %x" % (qemu_val, sim_val))
+        if qemu_val != sim_val:
+            log("expect fpr %d %x got %x" % (fpr, qemu_val, sim_val))
         #self.assertEqual(qemu_val, sim_val,
         #                 "expect %x got %x" % (qemu_val, sim_val))
     #self.assertEqual(qcr, sim_cr)