From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 21 Mar 2019 19:58:33 +0000 (+0000)
Subject: reduce args to FPAddStage0
X-Git-Tag: ls180-24jan2020~1555
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b19dbd13a6e89458f0ee19dad6eb199550e154a1;p=ieee754fpu.git

reduce args to FPAddStage0
---

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index a14ad01d..55438c2b 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -825,10 +825,10 @@ class FPAddStage0(FPState, FPID):
         self.mod = FPAddStage0Mod(width)
         self.o = self.mod.ospec()
 
-    def setup(self, m, in_a, in_b, in_mid):
+    def setup(self, m, i, in_mid):
         """ links module to inputs and outputs
         """
-        self.mod.setup(m, in_a, in_b)
+        self.mod.setup(m, i)
         if self.in_mid is not None:
             m.d.comb += self.in_mid.eq(in_mid)