From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 16 Dec 2019 22:39:13 +0000 (-0800)
Subject: Skip $inout transformation if not a PI
X-Git-Tag: working-ls180~881^2^2~78
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b19fc8839bdbf652d136790fe94cdaa1b520c75b;p=yosys.git

Skip $inout transformation if not a PI
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index c080cca4d..6ca24bd7e 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -542,10 +542,12 @@ struct XAigerWriter
 				undriven_bits.erase(bit);
 			}
 
-		// For inout ports, or keep-ed wires, then create a new wire with an
-		// $inout.out suffix, make it a PO driven by the existing inout, and
-		// inherit existing inout's drivers
+		// For inout ports, or keep-ed wires, that end up as both a PI and a
+		// PO, then create a new PO with an $inout.out suffix that is driven
+		// by the existing inout, and inherit its drivers
 		for (auto bit : inout_bits) {
+			if (!input_bits.count(bit))
+				continue;
 			RTLIL::Wire *wire = bit.wire;
 			RTLIL::IdString wire_name = stringf("$%s$inout.out", wire->name.c_str());
 			RTLIL::Wire *new_wire = module->wire(wire_name);