From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 24 May 2020 15:05:00 +0000 (+0100)
Subject: add stub regfiles.py
X-Git-Tag: div_pipeline~880
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b1a9215b81b6f74edbe814ba71714fb9ca4cd32b;p=soc.git

add stub regfiles.py
---

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
new file mode 100644
index 00000000..b848ea47
--- /dev/null
+++ b/src/soc/regfile/regfiles.py
@@ -0,0 +1,19 @@
+# POWER9 Register Files
+"""POWER9 regfiles
+
+Defines the following register files:
+
+    * INT regfile
+    * SPR regfile
+    * CR regfile
+    * XER regfile
+    * FAST regfile
+
+Links:
+
+* https://bugs.libre-soc.org/show_bug.cgi?id=345
+* https://libre-soc.org/3d_gpu/architecture/regfile/
+* https://libre-soc.org/openpower/isatables/sprs.csv
+"""
+
+# TODO