From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 28 Nov 2019 20:59:43 +0000 (-0800)
Subject: clkpart -unpart into 'finalize'
X-Git-Tag: working-ls180~881^2^2~114
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b1ab7c16c41f0a14b8b14a041367f2259b3c0e37;p=yosys.git

clkpart -unpart into 'finalize'
---

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 5bc55387b..554c42d68 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -538,16 +538,14 @@ struct SynthXilinxPass : public ScriptPass
 				else
 					abc9_opts += " -lut +/xilinx/abc9_xc7.lut";
 				run("abc9" + abc9_opts);
-				run("clean");
-				run("clkpart -unpart clkpart");
 			}
 			else {
 				if (nowidelut)
 					run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
 				else
 					run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
-				run("clean");
 			}
+			run("clean");
 
 			// This shregmap call infers fixed length shift registers after abc
 			//   has performed any necessary retiming
@@ -564,6 +562,9 @@ struct SynthXilinxPass : public ScriptPass
 		}
 
 		if (check_label("finalize")) {
+			if (help_mode || abc9)
+				run("clkpart -unpart clkpart", "(only if 'abc9')");
+
 			bool do_iopad = iopad || (ise && !noiopad);
 			if (help_mode || !noclkbuf) {
 				if (help_mode || do_iopad)