From: lkcl <lkcl@web>
Date: Tue, 14 Sep 2021 15:27:10 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~137
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b1b39501b45392708fdac0c65e7e5672cf4856f5;p=libreriscv.git

---

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 415588659..985c192cb 100644
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -5,8 +5,8 @@ Links:
 * <https://bugs.libre-soc.org/show_bug.cgi?id=687>
 * [[svp64]]
 * [[sv/branches]]
-* [[opnpower/isa/sprset]]
-* [[/openpower/isa/condition]]
+* [[openpower/isa/sprset]]
+* [[openpower/isa/condition]]
 
 Condition Register Fields are only 4 bits wide: this presents some
 interesting conceptual challenges for SVP64, particularly with respect to element