From: Clifford Wolf Date: Wed, 6 Mar 2019 04:47:07 +0000 (-0800) Subject: Improve igloo2 example X-Git-Tag: yosys-0.9~261 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b1b9edf5cc9e280346ffa0132d570a8ff656eb22;p=yosys.git Improve igloo2 example Signed-off-by: Clifford Wolf --- diff --git a/examples/igloo2/example.v b/examples/igloo2/example.v index 05b6ced5e..4a9486e50 100644 --- a/examples/igloo2/example.v +++ b/examples/igloo2/example.v @@ -24,13 +24,14 @@ module example ( assign {LED1, LED2, LED3, LED4} = outcnt ^ (outcnt >> 1); + // assign CA = counter[10]; // seg7enc seg7encinst ( // .seg({AA, AB, AC, AD, AE, AF, AG}), // .dat(CA ? outcnt[3:0] : outcnt[7:4]) // ); - assign {AA, AB, AC, AD, AE, AF, AG} = ~(7'b 100_0000 >> outcnt[7:4]); - assign CA = counter[10]; + assign {AA, AB, AC, AD, AE, AF, AG} = ~(7'b 100_0000 >> outcnt[6:4]); + assign CA = outcnt[7]; endmodule module seg7enc (