From: rishucoding <rishucoding@gmail.com>
Date: Mon, 2 Jul 2018 21:03:55 +0000 (+0530)
Subject: fixed bug : iocell_side_io0_cell_out is a reg, initial value is 0
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b1c72384d5d4572b9b49c95793768595befa308c;p=pinmux.git

fixed bug : iocell_side_io0_cell_out is a reg, initial value is 0
---

diff --git a/src/test_bsv/tests/test_pinmux.py b/src/test_bsv/tests/test_pinmux.py
index 61eb25f..fa569a7 100644
--- a/src/test_bsv/tests/test_pinmux.py
+++ b/src/test_bsv/tests/test_pinmux.py
@@ -6,15 +6,18 @@ from cocotb.result import TestFailure
 import random
 
 
+""" dut is design under test """
+
 @cocotb.test()
 def pinmux_basic_test(dut):
     """Test for 5 + 10"""
     yield Timer(2)
-
+    #mux selection lines, each input two bit wide
     dut.mux_lines_cell0_mux_in = 1
     dut.mux_lines_cell1_mux_in = 2
     dut.mux_lines_cell2_mux_in = 0
     yield Timer(2)
+    #enable input for mux
     dut.EN_mux_lines_cell0_mux = 1
     dut.EN_mux_lines_cell1_mux = 1
     dut.EN_mux_lines_cell2_mux = 1
@@ -22,12 +25,13 @@ def pinmux_basic_test(dut):
     yield Timer(2)
 
     # GPIO2-out test
+    # GPIO is inout peripheral
     dut.peripheral_side_gpioa_a2_out_in = 0
     dut.peripheral_side_gpioa_a2_outen_in = 1
 
     yield Timer(2)
 
-    if dut.iocell_side_io2_cell_out != 0:
+    if dut.iocell_side_io2_cell_out != 0: #output of iopad
         raise TestFailure(
             "gpioa_a2=0/mux=0/out=1 %s iocell_io2 != 0" %
             str(dut.iocell_side_io2_cell_out))
@@ -81,7 +85,7 @@ def pinmux_basic_test(dut):
 
     yield Timer(2)
 
-    if dut.iocell_side_io0_cell_out != 1:
+    if dut.iocell_side_io0_cell_out != 0:
         raise TestFailure(
             "uart_tx=1/mux=0/out=1 %s iocell_io0 != 1" %
             str(dut.iocell_side_io0_cell_out))