From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 16 Jun 2019 05:53:03 +0000 (+0100)
Subject: elaboratable cases
X-Git-Tag: ls180-24jan2020~993
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b1c74c0ad84d8490c37691e29b926dae433d409d;p=ieee754fpu.git

elaboratable cases
---

diff --git a/src/ieee754/fpadd/align.py b/src/ieee754/fpadd/align.py
index 381df1e5..0bb75e0a 100644
--- a/src/ieee754/fpadd/align.py
+++ b/src/ieee754/fpadd/align.py
@@ -2,7 +2,7 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Module, Signal
+from nmigen import Module, Signal, Elaboratable
 from nmigen.cli import main, verilog
 
 from ieee754.fpcommon.fpbase import FPNumOut, FPNumIn, FPNumBase
@@ -93,7 +93,7 @@ class FPAddAlignMulti(FPState):
             m.next = "add_0"
 
 
-class FPAddAlignSingleMod:
+class FPAddAlignSingleMod(Elaboratable):
 
     def __init__(self, width, id_wid):
         self.width = width
diff --git a/src/ieee754/fpadd/specialcases.py b/src/ieee754/fpadd/specialcases.py
index d6dea0ac..dadb4598 100644
--- a/src/ieee754/fpadd/specialcases.py
+++ b/src/ieee754/fpadd/specialcases.py
@@ -2,7 +2,7 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Module, Signal, Cat, Const
+from nmigen import Module, Signal, Cat, Const, Elaboratable
 from nmigen.cli import main, verilog
 from math import log
 
@@ -14,7 +14,7 @@ from ieee754.fpcommon.getop import FPADDBaseData
 from ieee754.fpcommon.denorm import (FPSCData, FPAddDeNormMod)
 
 
-class FPAddSpecialCasesMod:
+class FPAddSpecialCasesMod(Elaboratable):
     """ special cases: NaNs, infs, zeros, denormalised
         NOTE: some of these are unique to add.  see "Special Operations"
         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
diff --git a/src/nmutil/latch.py b/src/nmutil/latch.py
index 460661ba..84235ffa 100644
--- a/src/nmutil/latch.py
+++ b/src/nmutil/latch.py
@@ -82,14 +82,14 @@ def sr_sim(dut):
     yield
 
 def test_sr():
-    dut = SRLatch()
+    dut = SRLatch(llen=4)
     vl = rtlil.convert(dut, ports=dut.ports())
     with open("test_srlatch.il", "w") as f:
         f.write(vl)
 
     run_simulation(dut, sr_sim(dut), vcd_name='test_srlatch.vcd')
 
-    dut = SRLatch(sync=False)
+    dut = SRLatch(sync=False, llen=4)
     vl = rtlil.convert(dut, ports=dut.ports())
     with open("test_srlatch_async.il", "w") as f:
         f.write(vl)