From: lkcl <lkcl@web>
Date: Sun, 17 Apr 2022 10:31:16 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2762
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b1dbf9a41745e7314510f55cddf349a304235e61;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index 732e38d3f..2c160cdc9 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -63,6 +63,11 @@ Pages being developed and examples
 * [[sv/vector_ops]] Vector ops needed to make a "complete" Vector ISA
 * [[sv/av_opcodes]] scalar opcodes for Audio/Video
 * [[sv/byteswap]]
+* Twin targetted instructions (two registers out, one implicit)
+  Explanation of the rules for twin register targets
+  (implicit RS, FRS) explained in SVP4 [[sv/svp64/appendix]]
+  - [[isa/svfixedarith]]
+  - [[isa/svfparith]]
 * TODO: OpenPOWER [[openpower/transcendentals]]
 
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