From: Michael Nolan <mtnolan2640@gmail.com>
Date: Sun, 24 May 2020 15:15:54 +0000 (-0400)
Subject: Fix bpermd and make tests pass
X-Git-Tag: div_pipeline~878
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b1ef77873b4d85a740f25449a118ce8869f3ab63;p=soc.git

Fix bpermd and make tests pass
---

diff --git a/src/soc/fu/logical/bpermd.py b/src/soc/fu/logical/bpermd.py
index f9d6c102..dc086fae 100644
--- a/src/soc/fu/logical/bpermd.py
+++ b/src/soc/fu/logical/bpermd.py
@@ -60,7 +60,7 @@ class Bpermd(Elaboratable):
         perm = Signal(self.width, reset_less=True)
         rb64 = [Signal(1, reset_less=True, name=f"rb64_{i}") for i in range(64)]
         for i in range(64):
-            m.d.comb += rb64[i].eq(self.rb[i])
+            m.d.comb += rb64[i].eq(self.rb[63-i])
         rb64 = Array(rb64)
         for i in range(8):
             index = self.rs[8*i:8*i+8]
diff --git a/src/soc/fu/logical/main_stage.py b/src/soc/fu/logical/main_stage.py
index f85acebe..1b793199 100644
--- a/src/soc/fu/logical/main_stage.py
+++ b/src/soc/fu/logical/main_stage.py
@@ -45,6 +45,9 @@ class LogicalMainStage(PipeModBase):
 
         comb += o.ok.eq(1) # overridden if no op activates
 
+
+        m.submodules.bpermd = bpermd = Bpermd(64)
+
         ##########################
         # main switch for logic ops AND, OR and XOR, cmpb, parity, and popcount
 
@@ -132,9 +135,8 @@ class LogicalMainStage(PipeModBase):
 
             ###### bpermd #######
             with m.Case(InternalOp.OP_BPERM):
-                m.submodules.bpermd = bpermd = Bpermd(64)
                 comb += bpermd.rs.eq(a)
-                comb += bpermd.rb.eq(b)
+                comb += bpermd.rb.eq(self.i.b)
                 comb += o.data.eq(bpermd.ra)
 
             with m.Default():