From: Daniel Benusovich <flyingmonkeys1996@gmail.com>
Date: Mon, 22 Apr 2019 01:23:54 +0000 (-0700)
Subject: Use singal passed into plru rather than relying on internal signal
X-Git-Tag: div_pipeline~2195
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b20ec80c5f1fdd044e6313042930d558014677de;p=soc.git

Use singal passed into plru rather than relying on internal signal
---

diff --git a/TLB/src/ariane/tlb.py b/TLB/src/ariane/tlb.py
index 9bff30c5..61f99ce2 100644
--- a/TLB/src/ariane/tlb.py
+++ b/TLB/src/ariane/tlb.py
@@ -112,6 +112,7 @@ class TLB:
         #--------------
 
         p = PLRU(self.tlb_entries)
+        plru_tree = Signal(p.TLBSZ)
         m.submodules.plru = p
 
         # connect PLRU inputs/outputs
@@ -121,7 +122,9 @@ class TLB:
             en.append(tc[i].replace_en_i)
         m.d.comb += [Cat(*en).eq(p.replace_en_o), # output from PLRU into tags
                      p.lu_hit.eq(hitsel.i),
-                     p.lu_access_i.eq(self.lu_access_i)]
+                     p.lu_access_i.eq(self.lu_access_i),
+                     p.plru_tree.eq(plru_tree)]
+        m.d.sync += plru_tree.eq(p.plru_tree_o)
 
         #--------------
         # Sanity checks